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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05617-GMR

Name: SI5338C-B05617-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05617-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05617-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05617-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05617-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05617-GMR datasheet, SI5338C-B05617-GMR pinout, SI5338C-B05617-GMR application, or SI5338C-B05617-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5/1.8/2.5/3.3 V), any-frequency synthesis capability (0.16–710 MHz), spread-spectrum control, and PCIe Gen 4 jitter compliance.

Technical Context

The SI5338C-B05617-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input stage supports eight reference sources - including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - enabling flexible system clock tree design.

Each of the four output drivers features independent frequency, phase (±45 ns range, <20 ps step), voltage, and format configuration. The device supports glitchless frequency increment/decrement in 1 ppm steps via pin or I²C control, and zero-delay mode via external feedback - critical for low-latency timing in FPGA and processor clocking.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS)
Output Frequency Range	0.16–710 MHz; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Spread Spectrum	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate

Pinout & Package

SI5338C-B05617-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-compatible; independently configured frequency, format, and voltage
CLK1A / CLK1B	Differential Output Pair 1	Supports same formats/frequencies as CLK0; enables multi-domain clock distribution
CLK2A / CLK2B	Differential Output Pair 2	Configurable for PCIe Gen 4 (100 MHz HCSL) or Ethernet (125 MHz LVDS) timing
CLK3A / CLK3B	Differential Output Pair 3	Independent phase adjustment (<20 ps step) for skew-critical FPGA interfaces
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz; internal 100 Ω termination; optimized for low-jitter crystal or oscillator inputs
IN3 / IN4	Single-Ended Reference Inputs	CMOS/SSTL/HSTL-compatible; 5–350 MHz range; slew-rate sensitive for jitter performance
VDDO0–VDDO3	Per-Output Buffer Supplies	Enable mixed-voltage clock domains (e.g., 1.8 V FPGA core + 3.3 V legacy peripheral)
SCL / SDA	I²C/SMBus Interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt Output	Asserts on loss-of-lock or loss-of-signal; enables real-time clock health monitoring

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs, each programmable to any frequency from 0.16 to 710 MHz with true 0 ppm accuracy
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) in HCSL 100 MHz mode; validated per PCI-SIG Base Spec 4.0
Independent Per-Output Voltage Control	Each output buffer powered from dedicated VDDOx pin (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs
Glitchless Frequency Adjustment	1 ppm step size via PINC/FDEC pins or I²C; no output interruption during dynamic frequency scaling
Programmable Spread Spectrum	On any output: 0.5–5.0% down-spread, 33–63 kHz modulation - reduces EMI without altering timing margins
Zero-Delay Mode Support	External feedback path enables synchronous clock forwarding with sub-ns alignment to input reference

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Clocking
Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently phased outputs - two for SERDES lanes, one for management CPU, one for packet buffer controller. Use Value: Eliminates four discrete oscillators; achieves <100 ps inter-output skew and 0.7 ps RMS jitter, meeting IEEE 802.3bj jitter budgets.	Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and integrated GPU - all requiring compliant 100 MHz reference clocks. IC Role / Device Role / Timing Role: Primary PCIe timing source delivering four HCSL 100 MHz clocks with independent spread-spectrum control per slot. Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while enabling per-slot EMI reduction via independent SSC tuning.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: 4K/8K video encoder with SMPTE 2082 (12G-SDI) and AES67 audio-over-IP, demanding precise 74.25 MHz, 148.5 MHz, and 297 MHz timing. IC Role / Device Role / Timing Role: Master clock synthesizer generating three exact frequencies plus a 10 MHz house sync reference. Use Value: Delivers 0 ppm frequency accuracy and <20 ps phase step resolution for frame-accurate genlock and lip-sync alignment.	Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring multiple precisely skewed clocks for stimulus generation and capture. IC Role / Device Role / Timing Role: Configurable clock source providing four phase-adjustable outputs (100–400 MHz) to drive FPGA I/O banks and ADC/DAC interfaces. Use Value: Enables sub-ns timing calibration across channels via independent ±45 ns phase offset with <20 ps granularity.

Ethernet Switch Timing

PCIe Gen 4 Server Clocking

Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently phased outputs - two for SERDES lanes, one for management CPU, one for packet buffer controller.

Use Value: Eliminates four discrete oscillators; achieves <100 ps inter-output skew and 0.7 ps RMS jitter, meeting IEEE 802.3bj jitter budgets.

Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and integrated GPU - all requiring compliant 100 MHz reference clocks.

IC Role / Device Role / Timing Role: Primary PCIe timing source delivering four HCSL 100 MHz clocks with independent spread-spectrum control per slot.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while enabling per-slot EMI reduction via independent SSC tuning.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: 4K/8K video encoder with SMPTE 2082 (12G-SDI) and AES67 audio-over-IP, demanding precise 74.25 MHz, 148.5 MHz, and 297 MHz timing.

IC Role / Device Role / Timing Role: Master clock synthesizer generating three exact frequencies plus a 10 MHz house sync reference.

Use Value: Delivers 0 ppm frequency accuracy and <20 ps phase step resolution for frame-accurate genlock and lip-sync alignment.

Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring multiple precisely skewed clocks for stimulus generation and capture.

IC Role / Device Role / Timing Role: Configurable clock source providing four phase-adjustable outputs (100–400 MHz) to drive FPGA I/O banks and ADC/DAC interfaces.

Use Value: Enables sub-ns timing calibration across channels via independent ±45 ns phase offset with <20 ps granularity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same architecture and pinout; factory-programmed with fixed configuration (non-I²C reprogrammable)	Limited to pre-defined frequency sets; no runtime reconfiguration or spread-spectrum tuning	Select when production volume justifies OTP programming and field updates are unnecessary
LMK04832RHAR	Two PLLs + eight outputs; higher power (120 mA); supports JESD204B deterministic latency	Targeted at RF/data converter timing; includes dual-loop jitter cleaning not present in SI5338C-B05617-GMR	Select for JESD204B-compliant systems requiring sub-100 fs jitter cleaning, not general-purpose clock synthesis

Compared with Si5338A-B-GM and LMK04832RHAR, SI5338C-B05617-GMR uniquely balances field-programmability, ultra-low jitter (0.7 ps RMS), and compact 4×4 mm footprint - making it optimal for space-constrained, multi-protocol designs requiring post-silicon clock tuning.

Availability

SI5338C-B05617-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10/25 GbE switching platforms, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05617-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 product line was designed for high-performance, multi-protocol clock generation in data center, telecom, and broadcast infrastructure - emphasizing low jitter, flexible output configuration, and I²C-based field programmability.

FAQ

What is the maximum output frequency supported by SI5338C-B05617-GMR in LVPECL format?

The SI5338C-B05617-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in 25G/50G Ethernet and CPRI applications without external frequency multiplication.

Does SI5338C-B05617-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B05617-GMR meets PCIe Gen 4 SRNS requirements with 0.11–0.32 ps RMS jitter (typ/max) when configured with a PLL bandwidth of 2–4 MHz and CDR = 10 MHz, as specified in Table 12 of the datasheet.

Can SI5338C-B05617-GMR generate four different output frequencies simultaneously?

Yes, SI5338C-B05617-GMR uses four independent MultiSynth™ engines to synthesize four distinct frequencies simultaneously - ranging from 0.16 to 710 MHz - with true 0 ppm accuracy and no shared dividers or frequency constraints between outputs.

What is the function of the INTR pin on SI5338C-B05617-GMR?

The INTR pin on SI5338C-B05617-GMR is an open-drain interrupt output that asserts low upon detection of loss-of-lock (LOL) or loss-of-signal (LOS), enabling real-time clock health monitoring and system-level fault response without polling the I²C interface.

Is SI5338C-B05617-GMR compatible with ClockBuilder Pro software?

Yes, SI5338C-B05617-GMR is fully supported by Skyworks' ClockBuilder Pro software, which provides GUI-based configuration, real-time jitter simulation, register map generation, and .c/.h file export for embedded initialization - simplifying bring-up and validation of the SI5338C-B05617-GMR in custom designs.

SI5338C-B05617-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05617-GMR FAQ

1.How can I place an order for SI5338C-B05617-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05617-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05617-GMR reliable?

The price and inventory of SI5338C-B05617-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05617-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05617-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05617-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05617-GMR?

SI5338C-B05617-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05617-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05617-GMR?

For technical support, including SI5338C-B05617-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05617-GMR requirements.

6.How does Aetrix verify that SI5338C-B05617-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05617-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05617-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05617-GMR?

All SI5338C-B05617-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05617-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05617-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05617-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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