Skyworks Solutions Inc. SI5338C-B05639-GM

Overview

SI5338C-B05639-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C for high-reliability timing in FPGA and processor clocking systems.

For engineers reviewing the SI5338C-B05639-GM datasheet, SI5338C-B05639-GM pinout, SI5338C-B05639-GM application, or SI5338C-B05639-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), flexible input references (crystal, CMOS, SSTL/HSTL, differential), and 24-QFN package compatibility with PCIe, Ethernet, and broadcast video timing requirements.

Technical Context

The SI5338C-B05639-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input sources (IN1–IN6), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating up to four distinct output frequencies with true zero-ppm accuracy. Each output driver supports format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and per-output supply voltage control (VDDO0–VDDO3).

It features real-time frequency and phase adjustment via dedicated pins (FINC/FDEC, PINC/PDEC) with 1 ppm step resolution and <20 ps phase step accuracy, plus programmable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output. Loss-of-lock and loss-of-signal alarms are provided via the INTR pin.

Key Specifications

Pinout & Package

SI5338C-B05639-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View) and Section 7 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338C-B05639-GM, Si5332A-D05639-GM offers superior jitter and scalability but requires updated firmware and layout review, while ICS8430I-01LG provides pin-compatible drop-in replacement only for static clock trees - neither matches the SI5338C-B05639-GM's balance of programmability, jitter performance, and PCIe Gen 4 readiness.

Availability

SI5338C-B05639-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server designs, 10 GbE switching platforms, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338C-B05639-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple crystal oscillators and simplify timing architecture in PCIe, Ethernet, and FPGA-based platforms.

FAQ

What is the primary function of the SI5338C-B05639-GM?

The SI5338C-B05639-GM is an I²C-programmable quad clock generator that synthesizes four independent, precise output frequencies from a single reference input. It replaces up to four discrete oscillators in systems requiring flexible, low-jitter timing - such as PCIe Gen 4, 10 GbE, and broadcast video equipment - and is fully specified for operation from –40 to +85 °C.

Does the SI5338C-B05639-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B05639-GM is explicitly validated for PCIe Gen 4 Common Clock compliance with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines and measured using the Skyworks PCIe Clock Jitter Tool. Its jitter performance meets PCI-SIG Base Specification 4.0 rev. 0.5 requirements for 100 MHz HCSL outputs.

Can the SI5338C-B05639-GM generate different output formats simultaneously?

Yes, the SI5338C-B05639-GM supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS (156.25 MHz), CLK1A/B as HCSL (100 MHz), CLK2A/B as LVPECL (312.5 MHz), and CLK3A/B as CMOS (25 MHz). Each output bank has independent VDDO supply and format register control, enabling direct interface to heterogeneous logic families without external level shifters.

What is the minimum input frequency supported by the SI5338C-B05639-GM in PLL bypass mode?

In PLL bypass (clock buffer) mode, the SI5338C-B05639-GM supports input frequencies down to 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is functional only above 5 MHz - below that threshold, the INTR alarm will not assert during signal loss.

How is configuration performed for the SI5338C-B05639-GM?

Configuration of the SI5338C-B05639-GM is performed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The tool generates custom configuration files (.cbs), validates timing constraints, and supports field updates - all without requiring FPGA or microcontroller intervention. Pre-programmed OTP versions are also available.