Skyworks Solutions Inc. SI5338C-B05660-GMR

Overview

SI5338C-B05660-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C for high-reliability timing in FPGA and processor clocking systems.

For engineers reviewing the SI5338C-B05660-GMR datasheet, SI5338C-B05660-GMR pinout, SI5338C-B05660-GMR application, or SI5338C-B05660-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet use cases, and two field-tested alternative parts with documented technical and application differences.

Technical Context

The SI5338C-B05660-GMR implements a dual-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers per output channel. Each output supports integer or fractional frequency synthesis with <20 ps programmable phase step resolution.

It features I²C/SMBus configuration, loss-of-lock and loss-of-signal alarms, independent output voltage selection (1.5/1.8/2.5/3.3 V), and flexible spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation rate) on any output - all within a 4 × 4 mm 24-QFN package with 1.8/2.5/3.3 V core supply compatibility.

Key Specifications

Pinout & Package

SI5338C-B05660-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family layout and validated for signal integrity and thermal performance in high-speed clock distribution.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with SI5338C-B05660-GMR, Si5332A-D05660-GM offers superior jitter and integrated timing but higher cost and tooling complexity, while ICS853S01IAGLF provides simpler deployment at the expense of configurability and modern compliance - making SI5338C-B05660-GMR the optimal balance for PCIe/10GbE upgrade paths.

Availability

SI5338C-B05660-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE switch clocking, and FPGA-based broadcast video sync requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05660-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, networking, and broadcast equipment - emphasizing low jitter, multi-format flexibility, and PCIe/SONET/10GbE compliance.

FAQ

What is the core supply voltage range supported by the SI5338C-B05660-GMR?

The SI5338C-B05660-GMR supports three core supply voltages: 1.8 V (±5% to +10%), 2.5 V (±10%), and 3.3 V (±10%). These ranges are fully specified across the –40 to +85 °C operating temperature, with typical core current draw of 45 mA at 100 MHz on all outputs and 25 MHz reference clock. The device maintains full functionality and jitter performance across all three supply options.

Does the SI5338C-B05660-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B05660-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL outputs and appropriate PLL bandwidth settings. This compliance is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4, and applies to all four outputs simultaneously at 100 MHz.

How many independent output voltage rails does the SI5338C-B05660-GMR provide?

The SI5338C-B05660-GMR provides four independent output buffer supply rails - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows mixed-signal interfacing (e.g., LVDS at 2.5 V and CMOS at 1.8 V) without level shifters, and is explicitly defined in Table 3 and Section 3.4 of the Si5338 datasheet Rev. 1.6.

Can the SI5338C-B05660-GMR generate frequencies above 350 MHz on all four outputs simultaneously?

No. The SI5338C-B05660-GMR can generate frequencies above 350 MHz on only two outputs simultaneously - specifically Fvco/4 and Fvco/6 - as stated in Note 6 of Table 6. All four outputs support up to 350 MHz continuously; higher frequencies require allocation across the two available high-band synthesis paths, limiting concurrent >350 MHz use cases.

What is the minimum input frequency the SI5338C-B05660-GMR accepts in PLL bypass (buffer) mode?

In PLL bypass (clock buffer) mode, the SI5338C-B05660-GMR accepts input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal (LOS) detection is only functional above 5 MHz - a key design constraint documented in Table 6 Note 3 and Section 3.2 of the datasheet.