Skyworks Solutions Inc. SI5338C-B05692-GM
- Part No.:
- SI5338C-B05692-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05692-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B05692-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338C-B05692-GM datasheet, SI5338C-B05692-GM pinout, SI5338C-B05692-GM application, or SI5338C-B05692-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338C-B05692-GM implements a two-stage PLL architecture: a high-stability reference stage (VCO + N-divider) followed by four independent MultiSynth™ fractional-N synthesis stages (M0–M3), each feeding a configurable output driver. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rail (VDDO0–VDDO3), programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. External feedback mode enables zero-delay operation, while INTR pin delivers loss-of-lock and loss-of-signal status.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) under specified test conditions |
| Output Count & Type | 4 independent outputs - supports up to four differential (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL) clocks simultaneously |
| Frequency Range | 0.16–710 MHz - covers PCIe (100 MHz), Ethernet (125/156.25 MHz), Fibre Channel (212.5/141.7 MHz), and processor/FPGA clocking |
| Input Reference Options | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system-level clock sourcing |
| Supply Voltages | VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - supports mixed-voltage board designs with per-output level translation |
| Package | 24-pin QFN, 4 × 4 mm - space-constrained PCBs requiring high-density timing solutions |
| Operating Temperature | –40 to +85 °C - industrial-grade thermal range for embedded telecom and networking equipment |
Pinout & Package
SI5338C-B05692-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with DC coupling |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential output pairs | Four independent output channels; each pair configurable as LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supply rails | Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for mixed-signal interface compatibility |
| SCL, SDA | I²C/SMBus interface | Standard 2-wire serial programming; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
| VDD | Core supply | 1.8/2.5/3.3 V ±10% core power; PSRR optimized for noisy digital environments |
| GND, RSVD_GND | Ground connections | Multiple GND pins and reserved ground pad ensure low-impedance return path and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs via independent fractional-N dividers (M0–M3) |
| PCIe Gen 4 compliance | Meets PCIe Base Spec 4.0 rev. 0.5 jitter requirements (0.15–0.45 ps RMS) in common clock mode with 2–5 MHz PLL bandwidth |
| Independent phase adjustment | ±45 ns programmable offset per output in <20 ps steps - critical for skew-sensitive SerDes alignment |
| Spread spectrum control | Configurable on any output: 0.5–5.0% deviation, 33–63 kHz modulation rate - reduces EMI without affecting timing integrity |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled increment/decrement - enables real-time dynamic frequency scaling in FPGA/ASIC systems |
Applications
| PCIe Gen 4 Switch Timing | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: High-density server backplane with PCIe Gen 4 switches requiring ultra-low-jitter, multi-frequency clock distribution across multiple lanes. IC Role / Device Role / Timing Role: Quad clock generator providing four synchronized 100 MHz HCSL clocks with <0.45 ps RMS jitter for switch fabric and endpoint interfaces. Use Value: Eliminates need for four discrete oscillators; ensures PCIe Gen 4 common clock compliance and deterministic lane-to-lane skew. | Use Scenario: 10GbE line card in telecom aggregation router needing precise 156.25 MHz and 312.5 MHz clocks for PHY and MAC layers. IC Role / Device Role / Timing Role: Frequency translator generating integer-related outputs from a single 25 MHz crystal reference. Use Value: Reduces BOM count and layout complexity while maintaining sub-1 ps RMS jitter required for IEEE 802.3ae compliance. |
| Broadcast Video Frame Sync | FPGA-Based Video Processing |
Use Scenario: SMPTE ST 2082-1 compliant 12G-SDI video router requiring exact 27 MHz, 74.25 MHz, and 148.5 MHz clocks with tight phase alignment. IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering three independent outputs with programmable phase offsets (±45 ns) and <1 ps RMS jitter. Use Value: Enables frame-accurate genlock across multiple video processing paths without external delay lines or PLLs. | Use Scenario: High-throughput FPGA accelerator board using heterogeneous clock domains for DDR4 memory, PCIe host interface, and custom logic. IC Role / Device Role / Timing Role: Configurable clock source supplying 1200 MHz (DDR4), 250 MHz (PCIe), and 100 MHz (logic) from one device with independent voltage rails. Use Value: Simplifies power sequencing and eliminates inter-clock interference through isolated output buffers and dedicated VDDO supplies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B-GM | Same silicon die and pinout; factory-programmed with default register map (no OTP customization); lacks pre-configured B05692 firmware | Requires full I²C initialization at boot; not pre-validated for PCIe Gen 4 jitter or specific spread-spectrum profiles | Select when full runtime reconfiguration is needed and ClockBuilder Pro integration is available. |
| LMK04832ISQE/NOPB | Two PLLs (not four independent MultiSynth™ stages); higher power (120 mA vs. 45 mA typ); larger 48-QFN package | Supports JESD204B deterministic latency but lacks per-output spread spectrum and 1 ppm frequency step control | Select for deterministic delay applications in RF/data converter systems where dual-loop jitter cleanup is prioritized over output count and footprint. |
Compared with Si5338A-B-GM and LMK04832ISQE/NOPB, SI5338C-B05692-GM offers pre-validated PCIe Gen 4 jitter performance, smaller 24-QFN footprint, lower core current (45 mA), and unique per-output spread-spectrum control - making it optimal for space-constrained, multi-standard serial interface timing.
Availability
SI5338C-B05692-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line cards, broadcast video frame sync, and FPGA-based video processing requiring stable component supply and long-term lifecycle assurance.
Supply support for SI5338C-B05692-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line delivers high-performance, software-programmable clock generation for multi-standard serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple discrete oscillators with a single configurable IC.
FAQ
What is the primary function of the SI5338C-B05692-GM in a PCIe Gen 4 system?
The SI5338C-B05692-GM serves as a common clock generator delivering four ultra-low-jitter (0.15–0.45 ps RMS) 100 MHz HCSL clocks to PCIe Gen 4 switches and endpoints. Its pre-validated jitter performance, 2–5 MHz PLL bandwidth configuration, and SRNS compliance ensure full adherence to PCI-SIG Base Specification 4.0. SI5338C-B05692-GM eliminates the need for multiple discrete oscillators while maintaining deterministic skew across lanes.
Does the SI5338C-B05692-GM support spread-spectrum clocking (SSC) on individual outputs?
Yes, the SI5338C-B05692-GM supports independent spread-spectrum clocking on any output with user-selectable parameters: deviation (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). This capability is implemented per-output via dedicated registers and requires no external components. SI5338C-B05692-GM's SSC feature reduces electromagnetic interference without compromising timing margin in high-speed serial links like PCIe and SATA.
How does the SI5338C-B05692-GM handle loss-of-signal (LOS) and loss-of-lock (LOL) detection?
The SI5338C-B05692-GM integrates hardware-based LOS and LOL monitoring with configurable thresholds and response times. LOS detection activates within 2.6–5 µs of input clock failure; LOL detection responds in 5–10 ms after PLL unlock. Both events assert the open-drain INTR pin, enabling immediate system-level fault handling. SI5338C-B05692-GM also provides I²C-accessible status registers for precise root-cause analysis during debug or field diagnostics.
Can the SI5338C-B05692-GM generate non-integer-related output frequencies from a single reference?
Yes, the SI5338C-B05692-GM uses Skyworks' patented MultiSynth™ fractional-N synthesis to generate any frequency between 0.16 MHz and 710 MHz on each of its four outputs - even non-integer multiples of the input reference. For example, it can simultaneously synthesize 125 MHz (GbE), 156.25 MHz (10GbE), 212.5 MHz (Fibre Channel), and 312.5 MHz (PCIe Gen 4) from a single 25 MHz crystal. SI5338C-B05692-GM achieves true zero-ppm accuracy without external VCXOs or complex PLL loop filters.
What development tools are officially supported for configuring the SI5338C-B05692-GM?
Skyworks provides ClockBuilder Pro - a free, GUI-based configuration tool that supports SI5338C-B05692-GM register setup, jitter simulation, and I²C script generation. It integrates with standard USB-to-I²C adapters and validates configurations against PCIe Gen 4, Ethernet, and broadcast timing standards. SI5338C-B05692-GM also supports the Skyworks PCIe Clock Jitter Tool for real-time jitter measurement and compliance reporting per Intel and PCI-SIG specifications.
SI5338C-B05692-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05692-GM FAQ
1.How can I place an order for SI5338C-B05692-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05692-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05692-GM reliable?
The price and inventory of SI5338C-B05692-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05692-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B05692-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05692-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05692-GM?
SI5338C-B05692-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05692-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05692-GM?
For technical support, including SI5338C-B05692-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05692-GM requirements.
6.How does Aetrix verify that SI5338C-B05692-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05692-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05692-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B05692-GM?
All SI5338C-B05692-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05692-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05692-GM part is unused and in its original packaging.
Return procedure for SI5338C-B05692-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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