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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05692-GMR

Name: SI5338C-B05692-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05692-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05692-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05692-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05692-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and high-speed serial interface timing.

For engineers reviewing the SI5338C-B05692-GMR datasheet, SI5338C-B05692-GMR pinout, SI5338C-B05692-GMR application, or SI5338C-B05692-GMR equivalent, key selection criteria include PCIe Gen 4 SRNS jitter compliance (0.15 ps RMS), independent output voltage per driver (1.5–3.3 V), programmable phase/frequency step resolution (20 ps / 1 ppm), and flexible input support (crystal, CMOS, SSTL, differential up to 710 MHz).

Technical Context

The SI5338C-B05692-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output path includes configurable divider chains (R/M/N/P), selectable output format drivers, and per-channel voltage control (VDDO0–VDDO3).

It supports both free-running synthesis and synchronous frequency translation modes, with external feedback enabling zero-delay operation. Loss-of-lock and loss-of-signal monitoring, plus glitchless frequency/phase adjustment via dedicated pins or I²C, enable dynamic reconfiguration in live systems without clock interruption.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (0.15–0.45 ps RMS)
Output Frequency Range	0.16–710 MHz; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; validated for industrial and telecom line card environments
Power Consumption	45 mA typ core current at 100 MHz on all outputs and 25 MHz refclk

Pinout & Package

SI5338C-B05692-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDO supplies (VDDO0–VDDO3), core VDD, SCL/SDA/I²C interface, INTR alarm output, and ground/pad connections.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts AC-coupled LVDS/LVPECL/CML reference (5–710 MHz); internal 100 Ω termination enabled
CLK0A, CLK0B	Differential output pair 0	Configurable LVPECL/LVDS/HCSL/CML/CMOS; independent VDDO0 supply and format selection
VDDO0	Output buffer supply 0	Sets output swing and logic threshold for CLK0A/B; supports 1.5/1.8/2.5/3.3 V
SCL, SDA	I²C serial interface	Standard SMBus-compatible 2-wire bus (up to 400 kHz) for configuration and status readback
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal event

Key Features

Feature	Design Value
Independent multi-format outputs	Each of four outputs supports LVPECL, LVDS, HCSL, CML, SSTL, HSTL, or CMOS - no shared format constraints
Zero-ppm synthesis accuracy	MultiSynth™ fractional-N synthesis enables exact integer/fractional frequency generation with no accumulated error
Glitchless frequency tuning	Pin-controlled or I²C-based increment/decrement with 1 ppm step size and <667 ns update time above 18 MHz
Programmable phase offset	±45 ns range in 20 ps steps per output; enables deterministic skew alignment across multiple clock domains
Spread spectrum capability	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized, low-jitter reference clocks to PCIe Gen 4 switches and endpoint devices in data center top-of-rack systems. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS). Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.35 ps RMS jitter margin required for Gen 4 link training and stability.	Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and switch fabric interfaces. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing Ethernet-standard rates with identical jitter performance across all outputs. Use Value: Enables single-device clock tree for multi-rate Ethernet platforms, reducing BOM count and PCB area vs. discrete XO + divider solutions.
FPGA Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying core, I/O, transceiver, and DDR clock domains to Xilinx Versal or Intel Agilex FPGAs in compute-accelerated edge servers. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage per output (1.8 V for I/O, 1.2 V-equivalent for core via VDDO scaling). Use Value: Supports mixed-voltage FPGA clocking without level shifters; phase alignment ensures setup/hold timing closure across clock domains.	Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and auxiliary sync clocks in broadcast camera control units. IC Role / Device Role / Timing Role: High-frequency LVPECL clock generator with <10 ps cycle-cycle jitter and programmable phase for genlock alignment. Use Value: Meets SMPTE jitter limits (<0.2 UI) at 12G-SDI rates using direct synthesis - avoids jitter accumulation from PLL cascading.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized, low-jitter reference clocks to PCIe Gen 4 switches and endpoint devices in data center top-of-rack systems.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS).

Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.35 ps RMS jitter margin required for Gen 4 link training and stability.

Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and switch fabric interfaces.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing Ethernet-standard rates with identical jitter performance across all outputs.

Use Value: Enables single-device clock tree for multi-rate Ethernet platforms, reducing BOM count and PCB area vs. discrete XO + divider solutions.

FPGA Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying core, I/O, transceiver, and DDR clock domains to Xilinx Versal or Intel Agilex FPGAs in compute-accelerated edge servers.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage per output (1.8 V for I/O, 1.2 V-equivalent for core via VDDO scaling).

Use Value: Supports mixed-voltage FPGA clocking without level shifters; phase alignment ensures setup/hold timing closure across clock domains.

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and auxiliary sync clocks in broadcast camera control units.

IC Role / Device Role / Timing Role: High-frequency LVPECL clock generator with <10 ps cycle-cycle jitter and programmable phase for genlock alignment.

Use Value: Meets SMPTE jitter limits (<0.2 UI) at 12G-SDI rates using direct synthesis - avoids jitter accumulation from PLL cascading.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 5 × 5 mm 32-QFN package	Preferred for space-constrained designs requiring ultra-low jitter and crystal integration; not drop-in compatible due to pin count and footprint change	Select when crystal integration and sub-0.4 ps RMS jitter are mandatory, and PCB layout allows 32-pin QFN
ICS854S01IAGLF	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis, no I²C, 0.4 ps RMS jitter, 16-pin TSSOP	Only suitable for static clock distribution where frequencies are known and unchanging; lacks frequency translation or phase control	Choose only for cost-sensitive, fixed-rate applications where programmability is unnecessary and jitter budget is tighter than 0.7 ps

Compared with Si5332A-D06889-GM and ICS854S01IAGLF, SI5338C-B05692-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for mid-volume, multi-protocol systems requiring design flexibility without crystal integration overhead.

Availability

SI5338C-B05692-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, FPGA processor clocking, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05692-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems - targeting PCIe, Ethernet, Fibre Channel, and broadcast video infrastructure where jitter, flexibility, and footprint matter.

FAQ

What is the maximum output frequency supported by SI5338C-B05692-GMR in LVPECL mode?

The SI5338C-B05692-GMR supports up to 710 MHz in LVPECL output mode, as specified in Table 6 of the Skyworks datasheet. This applies when using differential outputs with appropriate termination and supply voltage (VDDO ≥ 2.5 V). Frequencies above 350 MHz require use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique values.

Does SI5338C-B05692-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338C-B05692-GMR is explicitly SRNS-compliant for PCIe Gen 4, achieving 0.11–0.32 ps RMS jitter under defined test conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This is verified in Table 12 of the official Skyworks datasheet Rev. 1.6 and confirmed via Skyworks' PCIe Clock Jitter Tool validation.

Can SI5338C-B05692-GMR generate different output voltages on each channel?

Yes, SI5338C-B05692-GMR provides independent VDDO supplies (VDDO0–VDDO3) for each output pair, supporting 1.5 V, 1.8 V, 2.5 V, or 3.3 V per channel. This enables mixed-voltage clocking - for example, 1.8 V LVDS for FPGA I/O banks and 2.5 V HCSL for PCIe slots - without external level shifters.

What input reference types does SI5338C-B05692-GMR accept?

SI5338C-B05692-GMR accepts five input reference types: (1) 8–30 MHz fundamental-mode crystal (differential), (2) CMOS (5–200 MHz), (3) SSTL/HSTL (5–350 MHz), and (4) differential (LVDS/LVPECL/CML, 5–710 MHz). All inputs support automatic loss-of-signal detection with configurable response times.

Is SI5338C-B05692-GMR pin-compatible with other Si5338 variants like SI5338A or SI5338B?

Yes, all Si5338 variants - including SI5338C-B05692-GMR - share identical 24-QFN pinout, electrical characteristics, and register map. The 'A', 'B', 'C' suffix denotes factory-programmed configuration (e.g., default output frequencies, I²C address, power-up behavior), not hardware differences. Hardware replacement is fully pin- and footprint-compatible.

SI5338C-B05692-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05692-GMR FAQ

1.How can I place an order for SI5338C-B05692-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05692-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05692-GMR reliable?

The price and inventory of SI5338C-B05692-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05692-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B05692-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05692-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05692-GMR?

SI5338C-B05692-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05692-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05692-GMR?

For technical support, including SI5338C-B05692-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05692-GMR requirements.

6.How does Aetrix verify that SI5338C-B05692-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05692-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05692-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B05692-GMR?

All SI5338C-B05692-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05692-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05692-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B05692-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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