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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05777-GM

Name: SI5338C-B05777-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05777-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05777-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05777-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B05777-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL architecture to synthesize four independent, zero-ppm-accurate output frequencies (0.16–710 MHz) with 0.7 ps RMS typical phase jitter. It supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs, operates from 1.8/2.5/3.3 V core supply, and targets PCIe Gen 1–4 timing in high-speed serial interfaces.

For engineers reviewing the SI5338C-B05777-GM datasheet, SI5338C-B05777-GM pinout, SI5338C-B05777-GM application, or SI5338C-B05777-GM equivalent, key selection criteria include differential output jitter compliance (PCIe Gen 4 SRNS), independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B05777-GM integrates two synthesis stages: a high-stability PLL (1.6 MHz loop bandwidth) locking to an external reference (8–30 MHz crystal or 5–710 MHz differential/CMOS input), followed by four independent MultiSynth™ fractional-N dividers enabling any-frequency synthesis per output. Each output driver is fully configurable for format, voltage, and termination.

It features loss-of-lock and loss-of-signal alarms, independent phase/frequency increment/decrement (20 ps / 1 ppm steps), and external feedback mode for zero-delay operation. The device uses on-chip OTP NVM for configuration storage and supports glitchless frequency transitions via pin or I²C control.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential outputs (CLK0A/B through CLK3A/B), configurable as up to eight single-ended clocks
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock and Gen 3 SRNS requirements
Frequency Range	0.16–710 MHz per output; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference inputs
Programmability	I²C/SMBus interface with ClockBuilder Pro GUI; OTP NVM stores configuration; no external EEPROM required
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range

Pinout & Package

SI5338C-B05777-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across Si5338 family variants; this part uses standard Si5338 pinout.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B through CLK3A/CLK3B	Differential output pairs	Four independent output drivers; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL
VDDO0–VDDO3	Output buffer supply pins	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz operation; supports write-protection and address selection
INTR	Interrupt output	Open-drain status indicator for loss-of-lock or loss-of-signal events; active-low assertion

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent output frequencies with true zero-ppm accuracy-no crystal-per-frequency required
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev 0.5 timing budget
Independent Output Voltage Control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs and ASICs
Glitchless Frequency Adjustment	Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption
Configurable Spread Spectrum	Per-output SSC with adjustable spread (0.5–5.0%), modulation rate (33–63 kHz), and center/down-spread mode
Zero-Delay Mode Support	External feedback path enables synchronous clock distribution with matched input-to-output propagation delay (~2.5 ns)

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks-one per switch port-with independent SSC control to reduce EMI. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and SRNS RMS jitter ≤0.32 ps, eliminating need for discrete oscillators per port.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a Layer-3 enterprise switch. IC Role / Device Role / Timing Role: Flexible frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates with sub-ps jitter. Use Value: Achieves GbE random jitter ≤0.79 ps RMS (1.875–20 MHz) and supports both IEEE 802.3 and ITU-T G.709 line rates.
Broadcast Video Frame Sync	FPGA-Based Video Processing
Use Scenario: Distributing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks across SDI transmitter/receiver modules in a 4K/8K video router. IC Role / Device Role / Timing Role: Precision clock synthesizer with programmable initial phase offset (±45 ns) and <20 ps phase step resolution for frame-accurate alignment. Use Value: Enables deterministic skew control between video processing paths, critical for SMPTE ST 2082-1 and ST 2110-10 compliance.	Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR interface clock, and 300 MHz transceiver reference to a Xilinx Versal ACAP in broadcast infrastructure. IC Role / Device Role / Timing Role: Configurable buffer and level translator supporting mixed-signal FPGA I/O banks (LVDS, HSTL, SSTL) from one compact IC. Use Value: Eliminates six discrete clock ICs; reduces BOM count and PCB area while maintaining <10 ps cycle-cycle jitter across all outputs.

PCIe Gen 4 Switch Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks-one per switch port-with independent SSC control to reduce EMI.

Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and SRNS RMS jitter ≤0.32 ps, eliminating need for discrete oscillators per port.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a Layer-3 enterprise switch.

IC Role / Device Role / Timing Role: Flexible frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates with sub-ps jitter.

Use Value: Achieves GbE random jitter ≤0.79 ps RMS (1.875–20 MHz) and supports both IEEE 802.3 and ITU-T G.709 line rates.

Broadcast Video Frame Sync

FPGA-Based Video Processing

Use Scenario: Distributing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks across SDI transmitter/receiver modules in a 4K/8K video router.

IC Role / Device Role / Timing Role: Precision clock synthesizer with programmable initial phase offset (±45 ns) and <20 ps phase step resolution for frame-accurate alignment.

Use Value: Enables deterministic skew control between video processing paths, critical for SMPTE ST 2082-1 and ST 2110-10 compliance.

Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR interface clock, and 300 MHz transceiver reference to a Xilinx Versal ACAP in broadcast infrastructure.

IC Role / Device Role / Timing Role: Configurable buffer and level translator supporting mixed-signal FPGA I/O banks (LVDS, HSTL, SSTL) from one compact IC.

Use Value: Eliminates six discrete clock ICs; reduces BOM count and PCB area while maintaining <10 ps cycle-cycle jitter across all outputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-A05783-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance	Targeted at ultra-low-jitter 100G/400G optical modules and AI accelerator cards where sub-0.4 ps RMS is mandatory	Select when >4 outputs or <0.4 ps RMS jitter is required; not drop-in due to different pinout and higher power (75 mA)
ICS8430I-01T	Fixed-frequency, non-programmable; 4 LVDS outputs only; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Suitable for cost-sensitive, static-clocking applications like legacy telecom line cards where frequency flexibility is unnecessary	Choose for simple, low-cost replacement where reprogramming is never needed and jitter budget allows ≥1.2 ps RMS

Compared with SI5338C-B05777-GM, the Si5332A-A05783-GM offers superior jitter and scalability but demands more board space and layout care, while the ICS8430I-01T trades programmability and jitter performance for simplicity and lower unit cost in fixed-rate systems.

Availability

SI5338C-B05777-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, broadcast video frame sync, and FPGA-based video processing requiring stable component supply and long-term design-in support.

Supply support for SI5338C-B05777-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-where precise frequency synthesis and multi-format output flexibility are essential.

FAQ

What is the maximum output frequency supported by SI5338C-B05777-GM in LVPECL mode?

The SI5338C-B05777-GM supports LVPECL outputs up to 710 MHz. This is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML formats. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper termination with 100 Ω differential load and careful layout to maintain jitter integrity. SI5338C-B05777-GM achieves this using its MultiSynth™ fractional-N synthesis engine.

Does SI5338C-B05777-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338C-B05777-GM meets PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Table 12 specifies 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) under SRNS test conditions with PLL bandwidth set to 2–4 MHz and CDR = 10 MHz. This compliance is validated using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-SIG Base Spec 4.0 rev 0.5. SI5338C-B05777-GM achieves this via optimized PLL loop filter and low-noise VCO design.

Can SI5338C-B05777-GM generate different output voltages on each of its four output banks?

Yes, SI5338C-B05777-GM provides independent VDDO0–VDDO3 supply pins, allowing each of the four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interface to mixed-voltage devices such as FPGAs with LVDS, SSTL, and HSTL I/O banks without level shifters. The datasheet confirms VDDOn range of 1.4–3.63 V and lists supported output formats per voltage in Table 6. SI5338C-B05777-GM implements this via dedicated LDO-like regulation per output stage.

Is an external EEPROM required to retain configuration on SI5338C-B05777-GM after power-down?

No, SI5338C-B05777-GM contains on-chip one-time-programmable (OTP) non-volatile memory that stores the full configuration. Upon power-up, it boots directly into the programmed state without requiring I²C initialization or external memory. ClockBuilder Pro software writes settings directly to OTP during programming. SI5338C-B05777-GM eliminates BOM cost and layout complexity associated with external EEPROMs while ensuring deterministic startup behavior.

What is the minimum input frequency supported for crystal operation on SI5338C-B05777-GM?

The SI5338C-B05777-GM supports crystal inputs from 8 MHz to 30 MHz, with specific load capacitance and ESR requirements segmented by frequency band (e.g., 8–11 MHz, 11–19 MHz, etc.). Table 8–11 confirm 8 MHz as the absolute minimum crystal frequency. Operation below 8 MHz is not supported in crystal mode, though the device accepts lower-frequency CMOS inputs (down to 5 MHz) via IN3/IN4. SI5338C-B05777-GM uses internal oscillator circuitry optimized for this 8–30 MHz range.

SI5338C-B05777-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05777-GM FAQ

1.How can I place an order for SI5338C-B05777-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05777-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05777-GM reliable?

The price and inventory of SI5338C-B05777-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05777-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05777-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05777-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05777-GM?

SI5338C-B05777-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05777-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05777-GM?

For technical support, including SI5338C-B05777-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05777-GM requirements.

6.How does Aetrix verify that SI5338C-B05777-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05777-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05777-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05777-GM?

All SI5338C-B05777-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05777-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05777-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05777-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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