Skyworks Solutions Inc. SI5338C-B05917-GM

Overview

SI5338C-B05917-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and PCIe timing applications.

For engineers reviewing the SI5338C-B05917-GM datasheet, SI5338C-B05917-GM pinout, SI5338C-B05917-GM application, or SI5338C-B05917-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338C-B05917-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports eight reference sources - including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - enabling flexible system clock sourcing.

Each output driver supports independent frequency (0.16–710 MHz), format, supply voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns, <20 ps step), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation). Loss-of-lock and loss-of-signal alarms, plus external feedback for zero-delay mode, support robust timing integrity in mission-critical systems.

Key Specifications

Pinout & Package

SI5338C-B05917-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D05917-GM and ICS853S01AGI-01LFT, SI5338C-B05917-GM delivers optimal balance of programmability, jitter performance, and pin-compatible scalability within the Si5338 family - making it ideal for PCIe Gen 4, multi-rate Ethernet, and FPGA clock trees requiring field-upgradable timing.

Availability

SI5338C-B05917-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/routing, and processor/FPGA clocking requiring stable component supply, long-lifecycle availability, and full traceability.

Supply support for SI5338C-B05917-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed to replace multiple discrete oscillators and clock buffers in high-speed digital systems, delivering programmable, low-jitter timing with minimal board space and power consumption.

FAQ

What is the maximum output frequency supported by SI5338C-B05917-GM?

The SI5338C-B05917-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per Skyworks Rev. 1.6 datasheet Table 6 note 6. This capability enables direct generation of PCIe 100 MHz, 10G Ethernet 156.25 MHz, and Fibre Channel 1.0625 GHz (via Fvco/4) without external dividers.

Does SI5338C-B05917-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B05917-GM meets PCIe Gen 4 Common Clock RMS jitter specification (≤0.45 ps RMS) as verified in Skyworks Rev. 1.6 datasheet Table 12. It achieves this with a 2–5 MHz PLL bandwidth and CDR = 10 MHz configuration, and is validated using the Skyworks PCIe Clock Jitter Tool. The device also satisfies Gen 1–3 requirements and SRNS compliance for Gen 3.

Can SI5338C-B05917-GM generate different output voltages on each channel?

Yes, SI5338C-B05917-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices - for example, driving 1.8 V FPGA transceivers, 2.5 V memory interfaces, and 3.3 V legacy peripherals - without external level shifters.

How is SI5338C-B05917-GM programmed, and what software is required?

SI5338C-B05917-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which provides GUI-based configuration, real-time jitter simulation, and one-click .c file generation. The tool auto-generates register maps and supports custom frequency plans, spread-spectrum settings, and phase offsets - eliminating manual register calculation for SI5338C-B05917-GM deployment.

What reference inputs does SI5338C-B05917-GM accept?

SI5338C-B05917-GM accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz; two single-ended pins (IN3, IN4) for CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz); and internal crystal oscillator support for 8–30 MHz crystals. All inputs feed into a flexible input multiplexer, allowing runtime switching between references for redundancy or multi-source systems.