Skyworks Solutions Inc. SI5338C-B05917-GMR
- Part No.:
- SI5338C-B05917-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05917-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,470
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338C-B05917-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338C-B05917-GMR datasheet, SI5338C-B05917-GMR pinout, SI5338C-B05917-GMR application, or SI5338C-B05917-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338C-B05917-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode with <1 ppb frequency resolution.
Its output stage provides per-driver configurability for signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), termination voltage (VDDOx = 1.4–3.63 V), and advanced features including independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and programmable spread spectrum on any output (33–63 kHz modulation rate, 0.5–5.0% spread).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 4 common clock RMS jitter requirement (≤0.45 ps typical) when configured per spec. |
| Output Frequency Range | 0.16–710 MHz - supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz. |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing. |
| Supply Voltages | VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board design with independent output driver rail control. |
| Package | 24-pin QFN, 4 × 4 mm - space-constrained PCBs benefit from compact footprint and thermal resistance θJA = 37 °C/W. |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments without derating. |
Pinout & Package
SI5338C-B05917-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2/3), IN5/IN6 (differential ref 4/5), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply rails), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential Output Pair 0 | Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz with independent VDDO0 voltage setting. |
| CLK1A / CLK1B | Differential Output Pair 1 | Independent frequency, format, and voltage vs. CLK0; enables multi-domain clocking (e.g., CPU + PCIe + DDR). |
| SCL / SDA | I²C Serial Interface | Standard SMBus-compatible 2-wire bus for configuration, status readback, and real-time frequency tuning. |
| INTR | Interrupt Output | Open-drain active-low signal indicating loss-of-lock or loss-of-signal events for system fault monitoring. |
| VDDO0–VDDO3 | Output Buffer Supplies | Four independent rails allow simultaneous LVDS (1.8 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (2.5 V) outputs. |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Four independent outputs each synthesize any frequency from 0.16 to 710 MHz with true zero-ppm accuracy via fractional-N synthesis. |
| PCIe Gen 1–4 Compliance | Meets Common Clock jitter specs (≤0.45 ps RMS for Gen 3/4) and SRNS requirements without external filtering or reclocking. |
| Independent Phase Adjustment | Programmable offset from –45 ns to +45 ns in <20 ps steps per output - enables precise timing alignment across multiple ASIC/FPGA domains. |
| Glitchless Frequency Tuning | Real-time 1 ppm step frequency increment/decrement via pin control or I²C - no output interruption during dynamic rate changes. |
| Flexible Spread Spectrum | Configurable down-spread (0.5–5.0%) at 33–63 kHz on any output - reduces EMI peak emissions without affecting system timing margins. |
Applications
| Ethernet Switch/Routing | PCIe Gen 1–4 Timing |
|---|---|
Use Scenario: High-density 1/10 GbE switch fabric requiring synchronized clocks for MAC, PHY, and packet buffer interfaces. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz (GbE), 156.25 MHz (10GbE), 250 MHz (PHY SerDes), and 100 MHz (control logic) clocks. Use Value: Eliminates four discrete oscillators; achieves sub-1 ps RMS jitter across all outputs to meet IEEE 802.3an and PCIe jitter budgets. | Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs sharing a common reference clock tree. IC Role / Device Role / Timing Role: PCIe Common Clock source delivering 100 MHz differential HCSL to root complex and endpoints while supporting SRNS mode for Gen 3. Use Value: Meets PCIe Gen 4 total jitter ≤33.6 ps pk-pk and RMS jitter ≤0.45 ps - validated using Intel Clock Jitter Tool per AN562. |
| Broadcast Video/Audio Timing | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/2081 video over IP gateway requiring genlock-capable, low-jitter reference distribution. IC Role / Device Role / Timing Role: Generates 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 1.544 MHz (T1 sync) from a single 25 MHz crystal. Use Value: MultiSynth™ zero-ppm synthesis ensures frame-accurate synchronization across multiple video processing pipelines. | Use Scenario: Xilinx Versal ACAP or Intel Agilex FPGA platform needing separate clocks for PL fabric, PS domain, transceivers, and DDR5 memory controller. IC Role / Device Role / Timing Role: Configurable quad clock source delivering 300 MHz (PL logic), 500 MHz (GT transceivers), 1200 MHz (DDR5 DFI), and 25 MHz (system management). Use Value: Independent VDDOx rails enable mixed-signal SoC integration (e.g., 1.8 V LVDS for transceivers, 1.1 V CMOS for logic) without level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05917-GM | Higher integration: integrated crystal option, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package (5 × 5 mm). | Targeted at next-gen PCIe 5.0 and CXL 2.0 systems requiring tighter jitter and more outputs; not drop-in compatible due to pin count and footprint change. | Select when upgrading from PCIe 4.0 to 5.0 infrastructure and board area permits larger package. |
| ICS853S01AG-01 | Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; 1.2 ps RMS jitter; 16-pin TSSOP package. | Only suitable for static clock fanout where frequencies are known and unchanging; lacks I²C interface, spread spectrum, or phase adjustment. | Choose only for cost-sensitive, fixed-clock-count applications with no frequency agility requirements. |
Compared with Si5332A-D05917-GM and ICS853S01AG-01, the SI5338C-B05917-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for mid-generation upgrades and space-constrained industrial designs where flexibility and proven interoperability matter most.
Availability
SI5338C-B05917-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338C-B05917-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and Fibre Channel - designed to replace multiple fixed-frequency oscillators with a single configurable IC.
FAQ
What is the maximum output frequency supported by SI5338C-B05917-GMR in LVPECL format?
The SI5338C-B05917-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability applies when operating in MultiSynth™ integer mode with appropriate VDDOx supply (≥2.5 V) and proper load termination (100 Ω differential). Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the synthesis architecture.
Does SI5338C-B05917-GMR support PCIe Gen 4 Common Clock mode with SRNS compliance?
Yes, SI5338C-B05917-GMR is explicitly stated as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in the official Skyworks documentation. Its measured RMS jitter of 0.15–0.45 ps (Table 12) meets PCIe Gen 4 specification requirements when configured with a 2–4 MHz PLL bandwidth and 10 MHz CDR, validated using the Skyworks PCIe Clock Jitter Tool.
Can SI5338C-B05917-GMR generate four different output frequencies simultaneously?
Yes, SI5338C-B05917-GMR uses four independent MultiSynth™ engines to generate four fully independent output frequencies - each configurable from 0.16 MHz to 710 MHz depending on format. The device achieves true zero-ppm precision on all outputs simultaneously, with no shared dividers or frequency constraints between channels.
What input reference options does SI5338C-B05917-GMR accept?
SI5338C-B05917-GMR accepts six input reference types: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL (5–350 MHz), HSTL (5–350 MHz), and differential (5–710 MHz) on pins IN1/IN2, IN5/IN6. IN3 and IN4 support single-ended CMOS inputs. All inputs include loss-of-signal detection with 2.6–5 µs response time.
Is ClockBuilder Pro software required to configure SI5338C-B05917-GMR?
No, ClockBuilder Pro is optional but strongly recommended for SI5338C-B05917-GMR configuration. The device supports full I²C/SMBus programming per register map (Section 6 of datasheet), enabling custom firmware integration. ClockBuilder Pro simplifies initial setup, jitter optimization, and PCIe compliance validation - but is not mandatory for basic functionality or production programming.
SI5338C-B05917-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05917-GMR FAQ
1.How can I place an order for SI5338C-B05917-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05917-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05917-GMR reliable?
The price and inventory of SI5338C-B05917-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05917-GMR is usually 5 days.
3.What payment methods are accepted for SI5338C-B05917-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05917-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05917-GMR?
SI5338C-B05917-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05917-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05917-GMR?
For technical support, including SI5338C-B05917-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05917-GMR requirements.
6.How does Aetrix verify that SI5338C-B05917-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05917-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05917-GMR meets industry standards.
7.What is the process for return or replacement of SI5338C-B05917-GMR?
All SI5338C-B05917-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05917-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05917-GMR part is unused and in its original packaging.
Return procedure for SI5338C-B05917-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338C-B05917-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

