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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B05953-GM

Name: SI5338C-B05953-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B05953-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B05953-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B05953-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B05953-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting PCIe Gen 1–4 and Ethernet switch timing in telecom and FPGA applications.

For engineers reviewing the SI5338C-B05953-GM datasheet, SI5338C-B05953-GM pinout, SI5338C-B05953-GM application, or SI5338C-B05953-GM equivalent, key selection factors include its 4× differential output capability, 0 ppm synthesis accuracy, PCIe Gen 4 SRNS compliance, 24-QFN package, and independent per-output voltage control (1.5/1.8/2.5/3.3 V).

Technical Context

The SI5338C-B05953-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) inputs.

Each of the four output pairs (CLK0A/B through CLK3A/B) offers independent frequency (0.16–710 MHz), format, output voltage (1.5–3.3 V), phase offset (±45 ns), and spread-spectrum control (0.5–5.0% at 33–63 kHz). Loss-of-lock and loss-of-signal alarms are integrated for system monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four differential output pairs (CLK0A/B to CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply Voltages	Core: 1.8/2.5/3.3 V; independent output buffers: 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports ClockBuilder Pro configuration

Pinout & Package

SI5338C-B05953-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS clock; VIH = 0.7×VDD, VIL = 0.3×VDD
IN5, IN6	Differential input pair 2	Second 5–710 MHz differential input; enables dual-reference redundancy or frequency translation
CLK0A, CLK0B	Differential output 0	Configurable LVPECL/LVDS/HCSL/CML; independent voltage (VDDO0) and format control
CLK1A, CLK1B	Differential output 1	Same configurability as CLK0; supports independent phase adjustment (<20 ps step)
CLK2A, CLK2B	Differential output 2	Independent frequency increment/decrement (1 ppm steps) via dedicated pins or I²C
CLK3A, CLK3B	Differential output 3	Enables spread spectrum (0.5–5.0%, 33–63 kHz) for EMI reduction on selected outputs
SCL, SDA	I²C serial interface	Configures all registers; supports ClockBuilder Pro GUI and in-system programming
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock (LOL) or loss-of-signal (LOS)
VDD, VDDO0–VDDO3	Power supplies	VDD = core supply (1.8/2.5/3.3 V); VDDOx = per-output buffer supply (1.5–3.3 V)
GND, RSVD_GND	Ground connections	Multiple GND pins and reserved ground pad ensure low-noise return paths and thermal dissipation

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable any-frequency generation (0.16–710 MHz) with true 0 ppm accuracy per output
PCIe Gen 4 SRNS compliance	0.11–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 separate-reference requirements
Per-output voltage control	Each output driver supports 1.5 V, 1.8 V, 2.5 V, or 3.3 V VDDO independently-enabling mixed-voltage system clocking
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption
Programmable phase offset	±45 ns adjustment per output with <20 ps resolution-critical for skew-sensitive SerDes alignment
Spread-spectrum clocking	Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz modulation) reduces EMI peak emissions

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Interconnect
Use Scenario: High-density 10/25/100 GbE switch fabric requiring synchronized clocks across multiple PHYs and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (management), and 250 MHz (CPU interface) clocks. Use Value: Eliminates four discrete oscillators; achieves sub-1 ps RMS jitter on all outputs to meet IEEE 802.3bj jitter budgets.	Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock and SRNS timing. IC Role / Device Role / Timing Role: Generates 100 MHz common reference and three independent 100 MHz SRNS clocks with matched phase alignment. Use Value: Meets PCIe Gen 4 SRNS RMS jitter limit (0.32 ps) while enabling dynamic frequency scaling via I²C during power-state transitions.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2059–2 compliant IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz genlock references. IC Role / Device Role / Timing Role: Synthesizes exact broadcast frequencies from a single 10 MHz GPSDO reference with zero ppm error. Use Value: Replaces crystal-based PLL modules; delivers <10 ps pk-pk period jitter essential for AES67 audio/video sync.	Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA, requiring multiple phase-aligned clocks (125 MHz, 250 MHz, 500 MHz, 1 GHz). IC Role / Device Role / Timing Role: Provides four precisely phased clocks with <20 ps step resolution for multi-rate test stimulus generation. Use Value: Enables deterministic clock domain crossing between FPGA logic, memory interfaces, and DACs without external delay lines.

Ethernet Switch Timing

PCIe Gen 4 Server Interconnect

Use Scenario: High-density 10/25/100 GbE switch fabric requiring synchronized clocks across multiple PHYs and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (management), and 250 MHz (CPU interface) clocks.

Use Value: Eliminates four discrete oscillators; achieves sub-1 ps RMS jitter on all outputs to meet IEEE 802.3bj jitter budgets.

Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage, and PLX switches demanding strict common-clock and SRNS timing.

IC Role / Device Role / Timing Role: Generates 100 MHz common reference and three independent 100 MHz SRNS clocks with matched phase alignment.

Use Value: Meets PCIe Gen 4 SRNS RMS jitter limit (0.32 ps) while enabling dynamic frequency scaling via I²C during power-state transitions.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2059–2 compliant IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz genlock references.

IC Role / Device Role / Timing Role: Synthesizes exact broadcast frequencies from a single 10 MHz GPSDO reference with zero ppm error.

Use Value: Replaces crystal-based PLL modules; delivers <10 ps pk-pk period jitter essential for AES67 audio/video sync.

Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA, requiring multiple phase-aligned clocks (125 MHz, 250 MHz, 500 MHz, 1 GHz).

IC Role / Device Role / Timing Role: Provides four precisely phased clocks with <20 ps step resolution for multi-rate test stimulus generation.

Use Value: Enables deterministic clock domain crossing between FPGA logic, memory interfaces, and DACs without external delay lines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05989-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs	Targeted at space-constrained systems where crystal footprint must be eliminated	Select when board area is critical and crystal BOM reduction is required; not drop-in due to different pinout and register map
ICS853S01IAGLF	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis, no I²C, 1.2 ps RMS jitter	Used only in static clock fanout scenarios with pre-defined frequencies	Choose only if design requires zero configuration, no frequency agility, and accepts higher jitter and no spread spectrum

Compared with Si5332A-D05989-GM, SI5338C-B05953-GM offers broader input flexibility and field-programmability but lacks integrated crystal; versus ICS853S01IAGLF, it provides full synthesis agility and jitter performance headroom at the cost of configuration complexity.

Availability

SI5338C-B05953-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server interconnects, Ethernet switch timing, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B05953-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The Si5338 product line delivers highly configurable, low-jitter clock generators for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where frequency agility and jitter performance are mission-critical.

FAQ

What is the maximum output frequency supported by SI5338C-B05953-GM?

The SI5338C-B05953-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz may be active simultaneously (Fvco/4 and Fvco/6), as specified in the functional description section of the datasheet.

Does SI5338C-B05953-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B05953-GM is explicitly validated for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz, meeting PCI Express Base Specification 4.0 rev. 0.5 requirements.

How is SI5338C-B05953-GM programmed, and what tools are required?

SI5338C-B05953-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software, which generates configuration files and supports real-time register editing, jitter simulation, and hardware validation. No external programmer is needed-only an I²C host or evaluation board with USB-to-I²C bridge.

Can SI5338C-B05953-GM generate four different output frequencies simultaneously?

Yes, SI5338C-B05953-GM uses four independent MultiSynth™ engines to synthesize four distinct frequencies simultaneously-from 0.16 MHz to 710 MHz-with 1 ppb resolution and 0 ppm accuracy. Each output can use different formats (e.g., LVDS, HCSL, CMOS) and supply voltages (1.5–3.3 V).

What is the thermal performance of SI5338C-B05953-GM in continuous operation?

SI5338C-B05953-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At typical 45 mA core current and full output load, junction temperature rise remains within safe limits up to +85 °C ambient, provided the exposed thermal pad is properly soldered to a ≥2 cm² copper pour.

SI5338C-B05953-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B05953-GM FAQ

1.How can I place an order for SI5338C-B05953-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B05953-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B05953-GM reliable?

The price and inventory of SI5338C-B05953-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05953-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B05953-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05953-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B05953-GM?

SI5338C-B05953-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B05953-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B05953-GM?

For technical support, including SI5338C-B05953-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05953-GM requirements.

6.How does Aetrix verify that SI5338C-B05953-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B05953-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05953-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B05953-GM?

All SI5338C-B05953-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05953-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B05953-GM part is unused and in its original packaging.

Return procedure for SI5338C-B05953-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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