Skyworks Solutions Inc. SI5338C-B05960-GMR

Overview

SI5338C-B05960-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B05960-GMR datasheet, SI5338C-B05960-GMR pinout, SI5338C-B05960-GMR application, or SI5338C-B05960-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage control (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe/10GbE/PCIe Gen 4 jitter compliance.

Technical Context

The SI5338C-B05960-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), 20 ps step resolution for phase increment/decrement, and glitchless frequency adjustment in 1 ppm steps.

Input reference options include external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clocks (5–710 MHz). Output drivers support independent supply voltages (VDDO0–VDDO3 = 1.5/1.8/2.5/3.3 V), spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and loss-of-lock/loss-of-signal alarms via INTR pin.

Key Specifications

Pinout & Package

SI5338C-B05960-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.6 datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B05960-GM, SI5338C-B05960-GMR offers full field reprogrammability via I²C without NVM constraints; versus LMK04832, it delivers superior frequency flexibility and lower power in consolidated timing architectures where jitter cleaning is secondary to synthesis precision.

Availability

SI5338C-B05960-GMR is available at Aetrix Electronics and suitable for Ethernet switch timing, PCIe Gen 4 clock distribution, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and guaranteed RoHS/halogen-free compliance.

Supply support for SI5338C-B05960-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators in high-speed digital systems, delivering programmable, low-jitter clock synthesis for PCIe, Ethernet, and broadcast infrastructure applications.

FAQ

What is the primary function of the SI5338C-B05960-GMR in a system design?

The SI5338C-B05960-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference. It replaces up to four discrete oscillators while supporting PCIe Gen 1–4, 10GbE, and broadcast video timing standards. Its MultiSynth™ architecture ensures true zero-ppm frequency accuracy on all outputs, making SI5338C-B05960-GMR ideal for consolidating timing resources in space-constrained, high-performance systems.

Does the SI5338C-B05960-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B05960-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. It is validated using the Skyworks PCIe Clock Jitter Tool and complies with PCI-SIG Base Specification 4.0 rev. 0.5. SI5338C-B05960-GMR achieves this with its two-stage PLL architecture and optimized MultiSynth™ synthesis, ensuring reliable link training and error-free operation in Gen 4 endpoints.

Can the SI5338C-B05960-GMR generate different output formats simultaneously?

Yes, the SI5338C-B05960-GMR supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS (100 MHz), CLK1A/B as HCSL (156.25 MHz), CLK2A/B as LVPECL (125 MHz), and CLK3A/B as CMOS (25 MHz). Each output driver is independently configurable for signal format, voltage (1.5/1.8/2.5/3.3 V), and termination. This eliminates external level shifters and simplifies SI5338C-B05960-GMR integration into heterogeneous interface environments.

How is the SI5338C-B05960-GMR programmed and configured?

The SI5338C-B05960-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequencies, formats, voltages, spread-spectrum parameters, phase offsets, and alarm thresholds. Factory NVM stores default settings, but SI5338C-B05960-GMR allows full runtime reconfiguration - critical for prototyping, field updates, and multi-platform reuse without hardware changes.

What thermal and power specifications apply to the SI5338C-B05960-GMR?

The SI5338C-B05960-GMR operates from –40 to +85 °C with a thermal resistance θJA of 37 °C/W (still air). Core supply current is 45 mA typical at 100 MHz on all outputs with a 25 MHz reference; output buffer current varies by format and frequency (e.g., 30 mA max for LVPECL at 710 MHz). Its 4 × 4 mm QFN package includes an exposed thermal pad for enhanced heat dissipation, ensuring stable SI5338C-B05960-GMR performance in thermally dense PCB layouts.