Skyworks Solutions Inc. SI5338C-B05973-GM
- Part No.:
- SI5338C-B05973-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B05973-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B05973-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338C-B05973-GM datasheet, SI5338C-B05973-GM pinout, SI5338C-B05973-GM application, or SI5338C-B05973-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338C-B05973-GM implements a two-stage PLL architecture: a reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode with <20 ps phase step accuracy and 1 ppm frequency increment/decrement.
Output drivers are fully decoupled-each supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats at frequencies from 0.16 MHz to 710 MHz (LVPECL/LVDS/CML), with independent VDDO supply (1.4–3.63 V) and programmable slew rate, termination, and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS) |
| Output Count & Type | 4 differential outputs (CLK0A/B through CLK3A/B); supports up to 8 single-ended or mixed configuration |
| Frequency Range | 0.16–710 MHz per output; 5–710 MHz input range with multiple interface options |
| Synthesis Resolution | 1 ppb; enables true zero-ppm accuracy on all outputs via MultiSynth™ fractional-N architecture |
| Supply Voltages | VDD core: 1.8/2.5/3.3 V ±10%; VDDO per output: 1.4–3.63 V independently configurable |
| Operating Temp | –40 to +85 °C; qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, exposed thermal pad |
Pinout & Package
SI5338C-B05973-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), four differential output pairs (CLK0A/B–CLK3A/B), three VDDO supplies (VDDO0–VDDO3), core VDD, SCL/SDA/I²C interface, INTR alarm, and reserved ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential Output Pair 0 | LVPECL/LVDS/HCSL-configurable; independently voltage- and format-controlled via VDDO0 |
| CLK1A / CLK1B | Differential Output Pair 1 | Supports same formats/frequencies as CLK0; isolated synthesis path ensures skew & jitter independence |
| CLK2A / CLK2B | Differential Output Pair 2 | Capable of 710 MHz LVPECL; requires AC coupling and 100 Ω differential termination |
| CLK3A / CLK3B | Differential Output Pair 3 | Programmable phase offset (±45 ns); used for deskew in multi-lane SerDes systems |
| IN1 / IN2, IN5 / IN6 | Differential Input Pairs | Accept 5–710 MHz AC-coupled signals; internal 10 kΩ bias and 3.5 pF capacitance |
| IN3 / IN4 | Single-Ended Inputs | Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| VDDO0–VDDO3 | Output Buffer Supplies | Independent 1.4–3.63 V rails per output pair; enable mixed-voltage system clocking |
| SCL / SDA | I²C Interface | Standard SMBus-compatible bus; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt Output | Open-drain status flag for loss-of-lock (LOL) and loss-of-signal (LOS) events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Synthesis | Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 1 ppb resolution and zero ppm error |
| PCIe Gen 4 Compliance | 0.15–0.45 ps RMS jitter in common clock mode; validated per PCIe Base Spec 4.0 rev 0.5 using Intel Clock Jitter Tool |
| Independent Output Control | Each output has dedicated VDDO, format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), slew rate, and spread-spectrum settings |
| Glitchless Frequency Tuning | Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption |
| Programmable Phase Offset | ±45 ns adjustment per output with <20 ps step accuracy; enables precise inter-lane deskew in 10G/25G Ethernet and PCIe |
| External Feedback Mode | Supports zero-delay buffer operation by routing CLKOUT back to feedback input, eliminating propagation delay in clock distribution trees |
Applications
| PCIe Gen 4 Switch Timing | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 switch ASICs and attached NVMe SSDs in data center servers. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (≤0.45 ps RMS) HCSL clocks meeting PCIe Gen 4 common clock jitter mask. Use Value: Eliminates need for four discrete oscillators; enables dynamic frequency margining and phase alignment across lanes via I²C. | Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE PHYs, MACs, and SerDes in telecom line cards. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae-compliant rates from a single 25 MHz crystal input. Use Value: Reduces BOM count and board area; supports dual-rate operation (10G/25G) with identical hardware footprint. |
| Broadcast Video Sync Generator | FPGA-Based Test Equipment |
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks to video encoders, decoders, and frame synchronizers. IC Role / Device Role / Timing Role: Precision clock generator with <20 ps phase step resolution for genlock and lip-sync alignment across multi-channel video pipelines. Use Value: Enables sub-frame timing accuracy; eliminates external PLLs and discrete VCXOs required for broadcast-grade synchronization. | Use Scenario: Supplying programmable clock sources (1–710 MHz) to FPGA logic, ADCs, DACs, and high-speed digital I/O in automated test equipment. IC Role / Device Role / Timing Role: Reconfigurable clock source supporting multiple instrument modes (e.g., pattern generator, logic analyzer, signal integrity tester) from one hardware platform. Use Value: Allows field-upgradable timing profiles via I²C; avoids hardware redesign when test requirements evolve. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05989-GM | Higher integration: includes integrated crystal, lower power (32 mA typ), tighter jitter (0.35 ps RMS), but fixed 4-output LVDS-only configuration | Best for space-constrained, crystal-less designs where LVDS-only outputs suffice and ultra-low jitter is mandatory | Select if crystal integration and sub-0.4 ps jitter outweigh flexibility in output format and voltage |
| ICS853S02IAGLF | Non-programmable, fixed-frequency quad LVDS generator (100/125/156.25 MHz); no I²C, no spread spectrum, higher jitter (1.2 ps RMS) | Suitable only for static, cost-sensitive applications with known fixed clock trees and relaxed jitter budgets | Choose only when design requires zero configuration effort and does not need frequency agility or PCIe Gen 4 compliance |
Compared with Si5332A-D05989-GM, SI5338C-B05973-GM trades slightly higher jitter and current draw for full I²C programmability, mixed-signal output flexibility, and external crystal support; versus ICS853S02IAGLF, it delivers 3× lower jitter, dynamic reconfiguration, and PCIe Gen 4 readiness at the cost of added software complexity.
Availability
SI5338C-B05973-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line card clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338C-B05973-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed for high-performance, software-defined clock generation in multi-protocol serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexible, low-jitter, and field-reprogrammable timing is critical.
FAQ
What is the primary function of the SI5338C-B05973-GM in a PCIe Gen 4 system?
The SI5338C-B05973-GM serves as a quad-output clock generator delivering four synchronized, low-jitter (≤0.45 ps RMS) reference clocks compliant with PCIe Gen 4 common clock specifications. It replaces discrete oscillators and enables dynamic frequency tuning, phase alignment, and spread-spectrum control-all programmable via I²C. Its MultiSynth™ architecture ensures zero-ppm accuracy on each SI5338C-B05973-GM output, critical for maintaining link integrity across high-speed PCIe lanes.
Does the SI5338C-B05973-GM support both differential and single-ended output formats?
Yes, the SI5338C-B05973-GM supports differential outputs (LVPECL, LVDS, HCSL, CML) and single-ended outputs (CMOS, SSTL, HSTL) on its four output pairs. Each output can be independently configured for format, voltage (1.5/1.8/2.5/3.3 V), and termination. Up to eight single-ended clocks may be generated simultaneously-or any combination of differential and single-ended-without hardware modification. This flexibility allows the SI5338C-B05973-GM to drive diverse loads including FPGAs, ASICs, and memory interfaces.
How is the SI5338C-B05973-GM programmed, and what tools are required?
The SI5338C-B05973-GM is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. ClockBuilder Pro provides GUI-based configuration of all parameters-including input selection, output frequencies, formats, voltages, spread-spectrum settings, and phase offsets-and generates register maps and initialization code. No external programmer is needed; configuration can be loaded at boot via EEPROM or dynamically during operation. The SI5338C-B05973-GM retains settings in one-time-programmable (OTP) memory, ensuring repeatable behavior across power cycles.
What input reference sources does the SI5338C-B05973-GM accept?
The SI5338C-B05973-GM accepts six input references: two differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz; two single-ended inputs (IN3/IN4) supporting CMOS/SSTL/HSTL at 5–350 MHz; and an on-chip oscillator supporting 8–30 MHz crystals. All inputs are automatically detected and selectable via register configuration. The SI5338C-B05973-GM's flexible input stage eliminates need for external level shifters or buffers in most applications, simplifying system-level clock tree design.
Is the SI5338C-B05973-GM suitable for industrial temperature applications?
Yes, the SI5338C-B05973-GM is rated for operation from –40 to +85 °C and is qualified for industrial environments. Its thermal resistance (θJA = 37 °C/W) and robust power supply rejection (PSRR) ensure stable performance under varying ambient conditions. The device maintains specified jitter, frequency accuracy, and output drive strength across this full range, making it suitable for deployment in telecom line cards, industrial Ethernet switches, and broadcast infrastructure where extended temperature reliability is mandatory. The SI5338C-B05973-GM's 24-QFN package includes an exposed thermal pad to enhance heat dissipation.
SI5338C-B05973-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B05973-GM FAQ
1.How can I place an order for SI5338C-B05973-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B05973-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B05973-GM reliable?
The price and inventory of SI5338C-B05973-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B05973-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B05973-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B05973-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B05973-GM?
SI5338C-B05973-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B05973-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B05973-GM?
For technical support, including SI5338C-B05973-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B05973-GM requirements.
6.How does Aetrix verify that SI5338C-B05973-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B05973-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B05973-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B05973-GM?
All SI5338C-B05973-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B05973-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B05973-GM part is unused and in its original packaging.
Return procedure for SI5338C-B05973-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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