Skyworks Solutions Inc. SI5338C-B05973-GMR

Overview

SI5338C-B05973-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338C-B05973-GMR datasheet, SI5338C-B05973-GMR pinout, SI5338C-B05973-GMR application, or SI5338C-B05973-GMR equivalent, key selection criteria include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, <20 ps phase step resolution, and PCIe Gen 4-compliant jitter performance at 100 MHz HCSL.

Technical Context

The SI5338C-B05973-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) followed by four independent MultiSynth™ fractional-N synthesis paths. Each path supports integer or fractional mode operation, enabling true zero-ppm accuracy and sub-ppb frequency resolution.

Its output stage provides full format and voltage configurability per driver-supporting LVPECL (0.16–710 MHz), LVDS (0.16–350 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), SSTL/HSTL (0.16–350 MHz)-with independent VDDO supplies (1.4–3.63 V) and programmable spread spectrum (0.5–5.0% deviation, 33–63 kHz modulation).

Key Specifications

Pinout & Package

SI5338C-B05973-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk 1/2), IN5/IN6 (diff clk 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D05973-GM and ICS8430I-01T, SI5338C-B05973-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact QFN - making it optimal for FPGA-based systems needing post-silicon clock tuning without redesign.

Availability

SI5338C-B05973-GMR is available at Aetrix Electronics and suitable for FPGA timing, PCIe Gen 4 server boards, and 10G/25G Ethernet switch designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B05973-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in FPGA, processor, and networking systems - emphasizing low jitter, software configurability, and flexible output formatting.

FAQ

What is the maximum output frequency supported by SI5338C-B05973-GMR in LVPECL format?

The SI5338C-B05973-GMR supports LVPECL outputs up to 710 MHz. However, only two unique frequencies above 350 MHz can be simultaneously generated - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints within the MultiSynth™ architecture. This limitation is documented in Section 3.3 of the datasheet.

Does SI5338C-B05973-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B05973-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical 0.11 ps) when configured with a PLL bandwidth of 2–4 MHz or 2–5 MHz and CDR = 10 MHz. This is verified per PCI Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool.

Can SI5338C-B05973-GMR generate different output voltages on each of its four drivers?

Yes, SI5338C-B05973-GMR supports independent output supply voltages per driver via dedicated VDDO0–VDDO3 pins. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling direct interface to mixed-voltage systems - for example, 1.8 V LVDS for an FPGA bank and 3.3 V CMOS for a legacy microcontroller.

What is the minimum input clock frequency supported by SI5338C-B05973-GMR in PLL bypass (buffer) mode?

In PLL bypass mode, SI5338C-B05973-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). Note that loss-of-signal detection is disabled below 5 MHz, as specified in Table 6 footnote 3 of the datasheet.

How is phase alignment controlled across the four outputs of SI5338C-B05973-GMR?

SI5338C-B05973-GMR provides independent programmable phase offset per output with ±45 ns range and <20 ps step resolution. Phase is adjusted digitally via register writes over I²C or hardware pins (PINC/FDEC), enabling precise skew calibration between SerDes lanes or memory channels without external delay lines.