Skyworks Solutions Inc. SI5338C-B06036-GM

Overview

SI5338C-B06036-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B06036-GM datasheet, SI5338C-B06036-GM pinout, SI5338C-B06036-GM application, or SI5338C-B06036-GM equivalent, key selection considerations include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control (0.5–5.0% deviation), and glitchless frequency adjustment in 1 ppm steps.

Technical Context

The SI5338C-B06036-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm accuracy across all outputs.

It features full I²C/SMBus programmability with nonvolatile memory (OTP), loss-of-lock and loss-of-signal alarms, independent phase offset (±45 ns, <20 ps step), and external feedback for zero-delay mode. Input reference range spans 5–710 MHz depending on interface type, while output frequencies reach up to 710 MHz (LVPECL/LVDS/CML), 350 MHz (SSTL/HSTL), 250 MHz (HCSL), or 200 MHz (CMOS).

Key Specifications

Pinout & Package

The SI5338C-B06036-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06089-GM and ICS853S01IAGLF, the SI5338C-B06036-GM offers optimal balance of field-programmability, jitter performance, and compact 24-QFN footprint-making it ideal for mid-volume, multi-standard designs requiring post-silicon clock tuning without footprint penalty.

Availability

SI5338C-B06036-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video synchronization, and FPGA processor clocking requiring stable component supply and long-term industrial lifecycle support.

Supply support for SI5338C-B06036-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in networking, computing, and broadcast equipment-emphasizing jitter performance, configurability, and PCIe/SONET/Ethernet standard compliance.

FAQ

What is the maximum output frequency supported by the SI5338C-B06036-GM in LVPECL format?

The SI5338C-B06036-GM supports LVPECL output frequencies up to 710 MHz. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as confirmed in Table 6 of the official datasheet. This limitation applies regardless of output format selection and is inherent to the MultiSynth™ architecture.

Does the SI5338C-B06036-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B06036-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) under specified test conditions (PLL BW 2–4 MHz, CDR = 10 MHz), as verified in Table 12 of the Skyworks datasheet Rev. 1.6. It also satisfies Gen 1–3 Common Clock and Gen 3 SRNS specifications.

Can the SI5338C-B06036-GM generate different output voltages on each driver?

Yes, the SI5338C-B06036-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output groups to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices such as multi-bank FPGAs without external level shifters, as detailed in Section 3.4 and Table 1 of the datasheet.

Is an external crystal required for SI5338C-B06036-GM operation?

No-an external crystal is optional. The SI5338C-B06036-GM accepts six input reference types: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz). Crystal use is common for stability, but system clocks or recovered clocks may serve as valid alternatives per functional block diagram and Table 6.

How is the SI5338C-B06036-GM programmed and configured?

The SI5338C-B06036-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates configuration files and supports OTP programming. Configuration includes output format, frequency, voltage, spread spectrum, and phase settings-all stored in on-chip nonvolatile memory for autonomous startup.