Skyworks Solutions Inc. SI5338C-B06036-GMR
- Part No.:
- SI5338C-B06036-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B06036-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,883
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338C-B06036-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and independent LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output configuration across four differential drivers. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338C-B06036-GMR datasheet, SI5338C-B06036-GMR pinout, SI5338C-B06036-GMR application, or SI5338C-B06036-GMR equivalent, key selection criteria include its 4× independent output format/frequency/voltage configurability, 24-QFN package footprint, PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), and I²C-based field reprogrammability without hardware changes.
Technical Context
The SI5338C-B06036-GMR integrates a dual-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each feeding a configurable output driver. Its synthesis resolution is 1 ppb, supporting any-frequency generation from 0.16 MHz to 710 MHz per output.
It supports flexible input references including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential signals. Output voltage per driver is independently set to 1.5/1.8/2.5/3.3 V, and each output supports glitchless ±1 ppm frequency increment/decrement and <20 ps phase step adjustment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS |
| Frequency range | 0.16–710 MHz per output; integer- or fractional-mode synthesis with 1 ppb resolution |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (0.15–0.45 ps RMS) |
| Input reference | Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential inputs |
| Supply voltages | Core: 1.8/2.5/3.3 V; output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp | –40 °C to +85 °C ambient, suitable for industrial and telecom line card environments |
Pinout & Package
SI5338C-B06036-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad (pin 24 = GND). Pin assignments follow standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), four differential output pairs (CLK0A/B–CLK3A/B), three VDDO supplies (VDDO0–VDDO3), core VDD (pins 9–10), SCL/SDA/I²C interface (pins 7–8), INTR alarm (pin 12), and reserved ground (pin 19).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential output pair 0 | Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz (LVPECL/LVDS), 0.16–250 MHz (HCSL) |
| CLK1A / CLK1B | Differential output pair 1 | Independent frequency/format/voltage control; same capability as CLK0A/B |
| CLK2A / CLK2B | Differential output pair 2 | Supports spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate) when enabled |
| CLK3A / CLK3B | Differential output pair 3 | Includes loss-of-lock and loss-of-signal status monitoring via INTR pin |
| SCL / SDA | I²C serial interface | Standard SMBus-compatible 2-wire bus for register programming and status readback |
| INTR | Interrupt output | Open-drain active-low signal indicating loss of lock, loss of signal, or other fault conditions |
| VDDO0–VDDO3 | Output buffer supply rails | Each powers one output pair; voltage selectable per driver (1.5/1.8/2.5/3.3 V) |
| VDD (pins 9,10) | Core supply | Single 1.8/2.5/3.3 V rail powering PLL, synthesizers, and logic; PSRR optimized |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs simultaneously |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter in common-clock mode satisfies PCIe Base Spec 4.0 rev 0.5 requirements |
| Glitchless frequency tuning | ±1 ppm frequency increment/decrement via pin or I²C with sub-1 ns update latency |
| Programmable phase offset | –45 ns to +45 ns initial phase adjustment per output with <20 ps step resolution |
| Flexible input support | Accepts crystal (8–30 MHz), single-ended (5–200 MHz), or differential (5–710 MHz) references without external circuitry |
Applications
| Processor and FPGA clocking | PCIe Gen 1–4 interconnect |
|---|---|
Use Scenario: Providing multiple synchronous clock domains for multi-core SoCs, Xilinx/Intel FPGAs, and ASICs requiring precise skew control and voltage-level translation. IC Role / Device Role / Timing Role: Quad-output programmable clock generator delivering independent frequencies (e.g., 100 MHz CPU, 200 MHz DDR, 300 MHz PCIe, 400 MHz SerDes) with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; enables dynamic reconfiguration of clock trees during system boot or runtime via I²C. | Use Scenario: Generating compliant reference clocks for PCIe root complexes, switches, and endpoints in servers, storage, and AI accelerators. IC Role / Device Role / Timing Role: PCIe Common Clock generator meeting Gen 3 SRNS and Gen 4 jitter specs (0.15–0.45 ps RMS) across all four lanes. Use Value: Passes Intel Clock Jitter Tool validation; supports both common-clock and separate-reference-no-spread (SRNS) modes without redesign. |
| Ethernet switch/router timing | Broadcast video/audio synchronization |
Use Scenario: Delivering low-jitter clocks to 1 GbE/10 GbE PHYs, packet processors, and traffic managers in carrier-grade switching platforms. IC Role / Device Role / Timing Role: Four-output clock source generating 125 MHz (GbE), 156.25 MHz (10GbE), 250 MHz (switch fabric), and 312.5 MHz (SerDes) simultaneously. Use Value: Meets IEEE 802.3 jitter limits; supports deterministic latency via programmable phase offsets between outputs. | Use Scenario: Synchronizing frame-accurate timing across SDI transmitters, video encoders, audio DACs, and genlock circuits in broadcast infrastructure. IC Role / Device Role / Timing Role: Any-frequency generator producing SMPTE ST 2059–2 PTP-aligned clocks (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) with sub-20 ps phase step control. Use Value: Enables frame-locked multi-channel video playback; supports external feedback for zero-delay mode in master-slave configurations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B-GM | Same silicon die and pinout; factory-programmed with fixed configuration (non-I²C reprogrammable) | Limited to pre-defined frequency sets; no field updates or dynamic tuning | Select when production volume justifies OTP programming and flexibility is unnecessary |
| LMK04832ISQE/NOPB | Two-stage jitter cleaner with integrated LDOs; higher power (120 mA core), larger 48-QFN package | Better additive jitter cleaning (<0.1 ps RMS) but lacks independent per-output voltage control and spread spectrum | Select when ultra-low additive jitter is critical and board space allows larger footprint |
Compared with Si5338A-B-GM and LMK04832ISQE/NOPB, SI5338C-B06036-GMR uniquely balances field-programmability, 4-output voltage independence, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for space-constrained, multi-protocol timing applications requiring post-production tuning.
Availability
SI5338C-B06036-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server interconnect, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338C-B06036-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for multi-protocol systems where space, power, and timing precision are critical-designed specifically for replacing multiple oscillators in FPGA, processor, and high-speed serial interface applications.
FAQ
What is the primary function of the SI5338C-B06036-GMR?
The SI5338C-B06036-GMR is a quad-output, I²C-programmable clock generator that synthesizes any frequency from 0.16 MHz to 710 MHz on each of its four differential outputs using Skyworks' MultiSynth™ technology. It serves as a drop-in replacement for up to four discrete crystal oscillators while enabling dynamic reconfiguration in-system. Its design centers on low-jitter timing for PCIe, Ethernet, and FPGA applications.
Does the SI5338C-B06036-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338C-B06036-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks AN562 guidelines. It is explicitly validated for PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliance, and jitter performance is verified using the Skyworks PCIe Clock Jitter Tool.
How many independent output voltage supplies does the SI5338C-B06036-GMR support?
The SI5338C-B06036-GMR supports four independent output buffer supply rails-VDDO0 through VDDO3-with each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous driving of mixed-logic-family loads (e.g., LVDS at 2.5 V and HCSL at 1.8 V) without external level shifters, a capability confirmed in the Si5338 datasheet Section 3.4.
Can the SI5338C-B06036-GMR generate spread-spectrum clocking (SSC) on individual outputs?
Yes, the SI5338C-B06036-GMR supports highly configurable spread-spectrum modulation on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and frequency range 5–350 MHz. SSC is independently enabled per output and does not affect other channels, allowing selective EMI reduction without compromising timing integrity elsewhere in the system.
What package type and pin count does the SI5338C-B06036-GMR use?
The SI5338C-B06036-GMR uses a 24-lead QFN package measuring 4 mm × 4 mm with 0.5 mm pitch and an exposed thermal pad (pin 24 = GND). This matches the standard Si5338 footprint defined in Skyworks Package Outline Document 9, and is confirmed in the "Device Pinout by Part Number" section (page 37) of the Rev. 1.6 datasheet.
SI5338C-B06036-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B06036-GMR FAQ
1.How can I place an order for SI5338C-B06036-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B06036-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B06036-GMR reliable?
The price and inventory of SI5338C-B06036-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B06036-GMR is usually 5 days.
3.What payment methods are accepted for SI5338C-B06036-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B06036-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B06036-GMR?
SI5338C-B06036-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B06036-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B06036-GMR?
For technical support, including SI5338C-B06036-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B06036-GMR requirements.
6.How does Aetrix verify that SI5338C-B06036-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338C-B06036-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B06036-GMR meets industry standards.
7.What is the process for return or replacement of SI5338C-B06036-GMR?
All SI5338C-B06036-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B06036-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B06036-GMR part is unused and in its original packaging.
Return procedure for SI5338C-B06036-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338C-B06036-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

