Skyworks Solutions Inc. SI5338C-B06043-GM

Overview

SI5338C-B06043-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for input references from 5 MHz to 710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338C-B06043-GM datasheet, SI5338C-B06043-GM pinout, SI5338C-B06043-GM application, or SI5338C-B06043-GM equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage control (1.5/1.8/2.5/3.3 V), independent phase/frequency increment/decrement capability, and 24-pin 4×4 mm QFN package with validated PCIe jitter performance.

Technical Context

The SI5338C-B06043-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ synthesis blocks, each driving one output pair (CLKxA/CLKxB). Each MultiSynth supports integer or fractional-N division with ≤1 ppb frequency resolution and <20 ps programmable phase step accuracy.

It accepts six input sources (IN1–IN6) - including differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and 8–30 MHz crystals - and routes any selected reference to any output path. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supply per bank and spread-spectrum modulation (0.5–5.0% down-spread, 33–63 kHz).

Key Specifications

Pinout & Package

SI5338C-B06043-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six inputs (IN1–IN6), four differential output pairs (CLK0A/B–CLK3A/B), four VDDO supplies (VDDO0–VDDO3), core VDD, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06189-GM, SI5338C-B06043-GM offers broader input reference support and simpler configuration for mid-jitter applications, while ICS853S02IAGLF provides lower unit cost but no programmability or PCIe timing certification.

Availability

SI5338C-B06043-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complex timing, FPGA-based compute acceleration, and telecom line card clocking requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338C-B06043-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed as a programmable, low-jitter clock generator platform for high-speed serial interface timing - specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video applications where flexible, accurate, and compliant clock synthesis is critical.

FAQ

What is the maximum output frequency supported by SI5338C-B06043-GM in LVPECL mode?

The SI5338C-B06043-GM supports LVPECL outputs up to 710 MHz, but only two unique frequencies above 350 MHz may be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. All other outputs are limited to ≤350 MHz in LVPECL mode per the datasheet's Table 6.

Does SI5338C-B06043-GM require an external crystal, or can it accept a single-ended clock input?

SI5338C-B06043-GM supports both: an 8–30 MHz fundamental-mode crystal connected to IN1/IN2, or a single-ended CMOS clock (5–200 MHz) applied to IN3 or IN4. The device auto-detects input type and configures the front-end accordingly; no external components are needed for CMOS input.

How is phase alignment achieved across multiple outputs of SI5338C-B06043-GM?

SI5338C-B06043-GM provides independent programmable initial phase offset (±45 ns range, <20 ps resolution) per output pair. When outputs derive from the same MultiSynth divider chain and use identical R-divider values, inter-output skew is guaranteed ≤100 ps (typical <30 ps) under matched loading and layout.

Is SI5338C-B06043-GM compliant with PCIe Gen 4 common clock specifications?

Yes - SI5338C-B06043-GM delivers ≤0.45 ps RMS jitter under PCIe Gen 4 common clock test conditions (PLL BW 2–5 MHz, CDR = 10 MHz), meeting the PCI-SIG Base Specification 4.0 requirement. This is verified using the Skyworks PCIe Clock Jitter Tool and Agilent 90804 oscilloscope measurements.

Can SI5338C-B06043-GM operate in clock buffer (PLL bypass) mode, and what is its additive jitter in that mode?

Yes - SI5338C-B06043-GM supports PLL bypass mode for low-latency clock forwarding. In this mode, additive phase jitter is 0.165 ps RMS (12 kHz–20 MHz) with a 622.08 MHz differential input, enabling ultra-low-noise fanout without synthesis artifacts.