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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B06074-GMR

Name: SI5338C-B06074-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B06074-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B06074-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B06074-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B06074-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL architecture to synthesize independent frequencies up to 710 MHz on four differential outputs with 0 ppm frequency accuracy, 0.7 ps RMS phase jitter (typ), and PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance. It serves as a single-chip replacement for multiple crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338C-B06074-GMR datasheet, SI5338C-B06074-GMR pinout, SI5338C-B06074-GMR application, or SI5338C-B06074-GMR equivalent, key selection criteria include its 4× independent output format configurability (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and support for differential input references up to 710 MHz.

Technical Context

The SI5338C-B06074-GMR integrates a two-stage synthesis architecture: a primary PLL with programmable loop bandwidth (1.6 MHz typ) locks to an external reference (crystal, CMOS, or differential), while four independent MultiSynth™ fractional-N synthesizers generate each output with sub-ppb resolution. Each output path includes configurable drivers, independent phase offset (<20 ps step), and glitchless frequency increment/decrement (1 ppm steps).

It supports flexible reference inputs - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential - and enables zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring over the I²C/SMBus interface.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential clock outputs (CLK0A/B through CLK3A/B)
Max Output Frequency	710 MHz (LVPECL/LVDS/CML); 350 MHz (SSTL/HSTL); 250 MHz (HCSL); 200 MHz (CMOS)
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz, LVDS/HCSL/LVPECL, 125 MHz output, 25 MHz ref)
Frequency Accuracy	True 0 ppm synthesis precision across all outputs using integer/fractional MultiSynth™
Supply Voltage	Core: 1.8 / 2.5 / 3.3 V (±10%); Output buffers: independently configurable 1.4–3.63 V
Operating Temp	–40 °C to +85 °C ambient, qualified for industrial and telecom applications
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B06074-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Reference Inputs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3/IN4	Single-Ended Reference Inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); IN3 active by default if both present
CLK0A/CLK0B – CLK3A/CLK3B	Differential Clock Outputs	Four fully independent pairs; each configurable for LVPECL, LVDS, HCSL, CML, SSTL, or HSTL
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output pair; enable mixed-voltage system interfacing
VDD	Core Supply	Single 1.8/2.5/3.3 V supply powering PLL, logic, and memory; excellent PSRR
SCL/SDA	I²C Interface	Standard SMBus-compatible 100/400 kHz interface; supports write-protection and interrupt-driven config
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration-complete events

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 0 ppm accuracy and <1 ppb resolution
PCIe Compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter requirements (0.11–0.45 ps RMS)
Per-Output Flexibility	Each output supports independent signal format, voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns, <20 ps step), and spread-spectrum (0.5–5.0%, 33–63 kHz)
Low-Power Operation	45 mA typical core current at 100 MHz on all outputs; buffer-only mode draws only 12 mA
Robust Monitoring	Integrated loss-of-lock (5–10 ms detect), loss-of-signal (2.6–5 µs), and programmable alarm outputs via INTR pin

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates four discrete oscillators and reduces board area by >60%; maintains deterministic inter-lane skew <100 ps across all outputs.	Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE PHYs and packet processors in a Layer 3 Ethernet switch. IC Role / Device Role / Timing Role: Frequency translator converting a 25 MHz crystal reference into multiple Ethernet-compliant rates with independent phase alignment. Use Value: Enables precise phase co-alignment of transmit/receive paths across ports; supports IEEE 1588 PTP timestamping via programmable initial phase offset.
Broadcast Video Frame Sync	FPGA-Based Telecom Line Card
Use Scenario: Delivering genlock-capable 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) clocks to video encoder/decoder ASICs in broadcast infrastructure. IC Role / Device Role / Timing Role: Any-frequency clock generator synthesizing SMPTE-compliant video rates from a single 10 MHz master reference. Use Value: Achieves <0.7 ps RMS jitter required for error-free 4K/60 video transport; eliminates need for separate VCXOs per video standard.	Use Scenario: Providing 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 1.25 GHz (CPRI) clocks to FPGA-based fronthaul processing units in 5G baseband cards. IC Role / Device Role / Timing Role: High-frequency clock synthesizer supporting multi-rate telecom standards with independent jitter-optimized outputs. Use Value: Meets OC-12 random jitter spec (≤0.7 ps RMS) and enables dynamic reconfiguration of CPRI rates via I²C without hardware change.

PCIe Gen 4 Switch Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS).

Use Value: Eliminates four discrete oscillators and reduces board area by >60%; maintains deterministic inter-lane skew <100 ps across all outputs.

Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE PHYs and packet processors in a Layer 3 Ethernet switch.

IC Role / Device Role / Timing Role: Frequency translator converting a 25 MHz crystal reference into multiple Ethernet-compliant rates with independent phase alignment.

Use Value: Enables precise phase co-alignment of transmit/receive paths across ports; supports IEEE 1588 PTP timestamping via programmable initial phase offset.

Broadcast Video Frame Sync

FPGA-Based Telecom Line Card

Use Scenario: Delivering genlock-capable 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) clocks to video encoder/decoder ASICs in broadcast infrastructure.

IC Role / Device Role / Timing Role: Any-frequency clock generator synthesizing SMPTE-compliant video rates from a single 10 MHz master reference.

Use Value: Achieves <0.7 ps RMS jitter required for error-free 4K/60 video transport; eliminates need for separate VCXOs per video standard.

Use Scenario: Providing 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 1.25 GHz (CPRI) clocks to FPGA-based fronthaul processing units in 5G baseband cards.

IC Role / Device Role / Timing Role: High-frequency clock synthesizer supporting multi-rate telecom standards with independent jitter-optimized outputs.

Use Value: Meets OC-12 random jitter spec (≤0.7 ps RMS) and enables dynamic reconfiguration of CPRI rates via I²C without hardware change.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06089-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC synchronization and high-channel-count systems where output count and ultra-low jitter are critical	Select when >4 outputs or sub-0.4 ps jitter is required; not drop-in due to different pinout and power architecture
ICS853S01AG-01LF	Fixed-function 4-output LVDS clock fanout buffer; no frequency synthesis, no I²C, no spread spectrum	Used only for clock distribution-not generation-where input and outputs share identical frequency and format	Choose only for simple fanout applications; cannot replace SI5338C-B06074-GMR in any-frequency synthesis or multi-format scenarios

Compared with Si5332A-D06089-GM and ICS853S01AG-01LF, the SI5338C-B06074-GMR uniquely balances programmability, jitter performance, and pin-compatible scalability within the Si5338 family-enabling field-upgradable timing without PCB redesign.

Availability

SI5338C-B06074-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, and broadcast video frame sync requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B06074-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338C-B06074-GMR belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-speed serial interface timing in datacenter, telecom, and broadcast equipment where multi-frequency synthesis, low jitter, and software-defined flexibility are essential.

FAQ

What is the maximum differential input frequency supported by the SI5338C-B06074-GMR?

The SI5338C-B06074-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This allows direct use of high-speed reference sources such as OC-192 or 10GBASE-R clocks without external division. Input slew rate must exceed 0.3 V/ns for optimal jitter performance, and a 100 Ω external termination resistor is required per differential pair.

Does the SI5338C-B06074-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B06074-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (1.5 MHz–50 MHz band) when configured for 100 MHz HCSL outputs and using recommended layout practices. Its PLL loop bandwidth (1.6 MHz typ) and MultiSynth™ architecture are validated per PCI-SIG Base Specification 4.0 rev. 0.5 test conditions.

Can the SI5338C-B06074-GMR generate four different output frequencies simultaneously?

Yes, the SI5338C-B06074-GMR synthesizes four independent output frequencies simultaneously - each configurable from 0.16 MHz to 710 MHz depending on format (e.g., 710 MHz for LVPECL, 200 MHz for CMOS). Frequencies are generated via dedicated MultiSynth™ blocks, enabling true any-frequency synthesis with zero ppm error and sub-ppb resolution.

What output voltage levels can be set independently for each output pair on the SI5338C-B06074-GMR?

Each output pair (CLK0, CLK1, CLK2, CLK3) on the SI5338C-B06074-GMR has its own VDDOx supply pin, allowing independent configuration of output buffer voltage between 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without level-shifting components.

How is the SI5338C-B06074-GMR programmed, and is factory programming available?

The SI5338C-B06074-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates custom configuration files and supports in-system reprogramming. Factory programming is available through Aetrix Electronics for pre-configured devices - including OTP NVM image loading - enabling plug-and-play deployment without host firmware involvement.

SI5338C-B06074-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B06074-GMR FAQ

1.How can I place an order for SI5338C-B06074-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B06074-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B06074-GMR reliable?

The price and inventory of SI5338C-B06074-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B06074-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B06074-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B06074-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B06074-GMR?

SI5338C-B06074-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B06074-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B06074-GMR?

For technical support, including SI5338C-B06074-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B06074-GMR requirements.

6.How does Aetrix verify that SI5338C-B06074-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B06074-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B06074-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B06074-GMR?

All SI5338C-B06074-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B06074-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B06074-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B06074-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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