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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B06163-GM

Name: SI5338C-B06163-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B06163-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B06163-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B06163-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B06163-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338C-B06163-GM datasheet, SI5338C-B06163-GM pinout, SI5338C-B06163-GM application, or SI5338C-B06163-GM equivalent, key selection criteria include its 0.7 ps RMS jitter (GbE), independent output voltage per driver (1.5–3.3 V), flexible input reference support (8–30 MHz crystal or 5–710 MHz differential), phase adjustment <20 ps step, and spread-spectrum capability (0.5–5.0% at 33–63 kHz).

Technical Context

The SI5338C-B06163-GM integrates two-stage PLL synthesis: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its architecture enables true any-frequency generation without external loop filters or VCO tuning components.

Each output driver supports independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent supply voltage (VDDO0–VDDO3), and independent phase/frequency increment/decrement control. The device includes loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and I²C/SMBus interface with ClockBuilder Pro configuration support.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent differential outputs (CLK0A/B to CLK3A/B) with optional single-ended mode via configuration
Frequency range	0.16–710 MHz per output; supports up to two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz, GbE test condition), enabling PCIe Gen 4 and 10 GbE timing compliance
Input reference	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments

Pinout & Package

SI5338C-B06163-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal biasing
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise clock generation
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz interface for register programming and status readback
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock and loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, zero-ppm-accuracy frequency generation on all four outputs without external components
PCIe Gen 4 common clock compliance	0.15–0.45 ps RMS jitter meets PCIe Base Spec 4.0 rev 0.5 requirements for 100 MHz HCSL outputs
Independent output voltage per driver	Allows direct interfacing to mixed-voltage SoCs, FPGAs, and ASICs without level-shifting circuitry
Programmable phase adjustment	±45 ns range with <20 ps step resolution enables precise skew alignment across multi-lane interfaces
Spread spectrum modulation	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output to reduce EMI in dense PCB layouts
External feedback mode	Supports zero-delay clock distribution by feeding back an output to the reference input path

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed PCIe Gen 4 switch IC requiring four synchronized 100 MHz clocks with sub-0.5 ps RMS jitter and common-clock topology. IC Role / Device Role / Timing Role: Primary clock generator providing PCIe REFCLK+ and REFCLK− to switch fabric and upstream/downstream ports. Use Value: Meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) and eliminates need for multiple discrete oscillators or complex PLL networks.	Use Scenario: 10 GbE/25 GbE line card with multi-port SerDes requiring low-jitter, format-flexible clocks for PHY and MAC layers. IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), and auxiliary clocks to FPGA and PHY devices. Use Value: Independent output format/voltage control allows direct connection to 1.8 V PHYs and 3.3 V legacy controllers without external buffers or level shifters.
Broadcast Video Timing	FPGA/ASIC Clocking
Use Scenario: SMPTE ST 2082 (12G-SDI) video processing board needing precise 297 MHz and 148.5 MHz clocks with tight phase alignment. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-compliant rates with programmable phase offset between outputs. Use Value: <20 ps phase step resolution enables sub-pixel timing alignment across parallel video lanes, critical for 4K/8K real-time processing.	Use Scenario: High-end FPGA-based test equipment requiring multiple independent clocks (e.g., 200 MHz logic, 125 MHz DDR, 100 MHz PCIe, 50 MHz ADC sampling). IC Role / Device Role / Timing Role: Single-chip clock source replacing four discrete oscillators and reducing BOM count, layout area, and power consumption. Use Value: 45 mA typical core current and 4 × 4 mm footprint minimize thermal load and PCB space versus discrete oscillator solutions.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed PCIe Gen 4 switch IC requiring four synchronized 100 MHz clocks with sub-0.5 ps RMS jitter and common-clock topology.

IC Role / Device Role / Timing Role: Primary clock generator providing PCIe REFCLK+ and REFCLK− to switch fabric and upstream/downstream ports.

Use Value: Meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) and eliminates need for multiple discrete oscillators or complex PLL networks.

Use Scenario: 10 GbE/25 GbE line card with multi-port SerDes requiring low-jitter, format-flexible clocks for PHY and MAC layers.

IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz (10GBase-R), 312.5 MHz (25GBase-R), and auxiliary clocks to FPGA and PHY devices.

Use Value: Independent output format/voltage control allows direct connection to 1.8 V PHYs and 3.3 V legacy controllers without external buffers or level shifters.

Broadcast Video Timing

FPGA/ASIC Clocking

Use Scenario: SMPTE ST 2082 (12G-SDI) video processing board needing precise 297 MHz and 148.5 MHz clocks with tight phase alignment.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-compliant rates with programmable phase offset between outputs.

Use Value: <20 ps phase step resolution enables sub-pixel timing alignment across parallel video lanes, critical for 4K/8K real-time processing.

Use Scenario: High-end FPGA-based test equipment requiring multiple independent clocks (e.g., 200 MHz logic, 125 MHz DDR, 100 MHz PCIe, 50 MHz ADC sampling).

IC Role / Device Role / Timing Role: Single-chip clock source replacing four discrete oscillators and reducing BOM count, layout area, and power consumption.

Use Value: 45 mA typical core current and 4 × 4 mm footprint minimize thermal load and PCB space versus discrete oscillator solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06163-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package	Better suited for ultra-low-jitter applications (e.g., optical transport, 5G fronthaul) where board space permits	Select when absolute lowest jitter and crystal integration outweigh cost and size constraints
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 1.2 ps RMS jitter; 3.3 V only	Limited to static clock fanout; no frequency translation or spread spectrum	Select only for simple clock distribution where frequency flexibility is unnecessary and cost is primary concern

Compared with Si5332A-D06163-GM, SI5338C-B06163-GM offers smaller footprint and lower cost but higher jitter and no integrated crystal; compared with ICS853S01AGI-01LFT, it provides full programmability and multi-format support at the expense of higher complexity and unit cost.

Availability

SI5338C-B06163-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25 GbE routing, broadcast video synchronization, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B06163-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-output clock generation in datacenter, telecom, and broadcast systems-emphasizing low jitter, programmability, and flexible I/O voltage support without external components.

FAQ

What is the maximum output frequency supported by SI5338C-B06163-GM?

The SI5338C-B06163-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as specified in the functional description and Table 6 of the datasheet. All outputs maintain 0 ppm accuracy within their respective ranges.

Does SI5338C-B06163-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B06163-GM is explicitly validated for PCIe Gen 4 Common Clock compliance, achieving 0.15–0.45 ps RMS jitter (12 kHz–20 MHz) on 100 MHz HCSL outputs with PLL bandwidth set to 2–4 or 2–5 MHz and CDR = 10 MHz, per PCI-Express Base Specification 4.0 rev 0.5 and Skyworks' AN562 test methodology.

Can SI5338C-B06163-GM generate different output formats simultaneously?

Yes, SI5338C-B06163-GM supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as CMOS, and CLK3A/B as SSTL-all independently configured via I²C registers. Each output bank (VDDO0–VDDO3) supports voltage-independent format selection per Skyworks' functional description section 3.4.

What is the minimum input crystal frequency supported by SI5338C-B06163-GM?

The SI5338C-B06163-GM supports external crystals from 8 to 30 MHz, with specific load capacitance recommendations (17–19 pF) and ESR limits (≤300 Ω for 8–11 MHz, ≤75 Ω for 26–30 MHz). Crystals below 8 MHz are not supported; alternative input sources (CMOS, differential) start at 5 MHz but require external buffering or termination.

How is phase alignment controlled across outputs in SI5338C-B06163-GM?

SI5338C-B06163-GM provides independent programmable initial phase offset (–45 to +45 ns) and phase increment/decrement control on each output with <20 ps step resolution. Alignment is achieved via register writes to the PHASE_OFFSETx registers, verified using the ClockBuilder Pro software and validated in the "Programmable Initial Phase Offset" section (page 27) of the datasheet.

SI5338C-B06163-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B06163-GM FAQ

1.How can I place an order for SI5338C-B06163-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B06163-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B06163-GM reliable?

The price and inventory of SI5338C-B06163-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B06163-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B06163-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B06163-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B06163-GM?

SI5338C-B06163-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B06163-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B06163-GM?

For technical support, including SI5338C-B06163-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B06163-GM requirements.

6.How does Aetrix verify that SI5338C-B06163-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B06163-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B06163-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B06163-GM?

All SI5338C-B06163-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B06163-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B06163-GM part is unused and in its original packaging.

Return procedure for SI5338C-B06163-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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