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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B06163-GMR

Name: SI5338C-B06163-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B06163-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B06163-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B06163-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338C-B06163-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B06163-GMR datasheet, SI5338C-B06163-GMR pinout, SI5338C-B06163-GMR application, or SI5338C-B06163-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338C-B06163-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode with <20 ps phase step resolution and 1 ppm frequency increment/decrement.

Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, with independent VDDO supplies enabling mixed-voltage clock distribution. The device supports external feedback for zero-delay mode and includes loss-of-lock and loss-of-signal alarms for system monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common clock jitter requirement (≤0.45 ps RMS) when configured per spec
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and processor clocks
Input Reference Support	8–30 MHz crystal or 5–710 MHz differential - enables direct use of low-cost crystals or high-speed SerDes reference clocks
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows mixed-signal SoC interfacing without level shifters
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-QFN, 4 × 4 mm - space-constrained FPGA/ASIC timing applications with thermal resistance θJA = 37 °C/W
Core Current (Typ)	45 mA at 100 MHz on all outputs - enables low-power clock tree design vs. discrete oscillator solutions

Pinout & Package

SI5338C-B06163-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended inputs	Support 5–200 MHz CMOS or 5–350 MHz SSTL/HSTL; internally biased
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDO supply
VDDO0–VDDO3	Output buffer supplies	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for mixed-interface systems
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz control; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status flag for loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency outputs (0.16–710 MHz) with true zero-ppm accuracy via fractional-N PLLs
PCIe Gen 4 compliance	Meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps) with 2–5 MHz PLL bandwidth and CDR = 10 MHz
Independent phase adjustment	±45 ns range in <20 ps steps per output - enables precise skew management across multi-lane interfaces
Spread spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts
External feedback mode	Enables zero-delay clock distribution - critical for synchronous backplane timing and deterministic latency paths

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a server motherboard. IC Role / Device Role / Timing Role: Quad clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 jitter spec (0.15–0.45 ps RMS) and enabling dynamic frequency margining via I²C.	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR/KR4 PHYs and MACs in telecom line cards. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae/3ba rates with sub-ppm accuracy and low additive jitter. Use Value: Achieves <0.7 ps RMS jitter at 156.25 MHz - below 10GbE random jitter limit - using internal MultiSynth™ without external filtering.
FPGA-Based Broadcast Video Sync	MSAN/DSLAM System Clock Tree
Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) pixel clock derivatives (e.g., 74.25 MHz, 148.5 MHz) to FPGA-based video processing pipelines. IC Role / Device Role / Timing Role: Configurable quad clock source supporting LVDS and HCSL outputs at mixed voltages for FPGA I/O banks. Use Value: Delivers <10 ps cycle-cycle jitter at 148.5 MHz - essential for error-free 4K/8K video sampling - with per-output voltage control (1.8 V LVDS, 3.3 V CMOS).	Use Scenario: Centralized clock generation for multi-port DSLAM line cards requiring 4 kHz, 19.44 MHz, and 155.52 MHz clocks for ATM, SONET, and PON subsystems. IC Role / Device Role / Timing Role: Frequency translator converting a single 25 MHz crystal into OC-12, E1, and GPON timing references. Use Value: Replaces three separate clock ICs; maintains OC-12 random jitter ≤0.7 ps RMS at 155.52 MHz while supporting simultaneous 4 kHz low-frequency output.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a server motherboard.

IC Role / Device Role / Timing Role: Quad clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment.

Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 jitter spec (0.15–0.45 ps RMS) and enabling dynamic frequency margining via I²C.

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR/KR4 PHYs and MACs in telecom line cards.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3ae/3ba rates with sub-ppm accuracy and low additive jitter.

Use Value: Achieves <0.7 ps RMS jitter at 156.25 MHz - below 10GbE random jitter limit - using internal MultiSynth™ without external filtering.

FPGA-Based Broadcast Video Sync

MSAN/DSLAM System Clock Tree

Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) pixel clock derivatives (e.g., 74.25 MHz, 148.5 MHz) to FPGA-based video processing pipelines.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting LVDS and HCSL outputs at mixed voltages for FPGA I/O banks.

Use Value: Delivers <10 ps cycle-cycle jitter at 148.5 MHz - essential for error-free 4K/8K video sampling - with per-output voltage control (1.8 V LVDS, 3.3 V CMOS).

Use Scenario: Centralized clock generation for multi-port DSLAM line cards requiring 4 kHz, 19.44 MHz, and 155.52 MHz clocks for ATM, SONET, and PON subsystems.

IC Role / Device Role / Timing Role: Frequency translator converting a single 25 MHz crystal into OC-12, E1, and GPON timing references.

Use Value: Replaces three separate clock ICs; maintains OC-12 random jitter ≤0.7 ps RMS at 155.52 MHz while supporting simultaneous 4 kHz low-frequency output.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06163-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (different default frequencies)	Pre-programmed for alternate frequency sets; requires reprogramming for identical behavior	Select if pre-configured startup frequencies match legacy designs; otherwise SI5338C-B06163-GMR offers identical hardware functionality
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; no spread spectrum or phase adjust	Limited to static clock trees; unsuitable for PCIe Gen 4 or dynamic frequency tuning	Choose only for cost-sensitive, fixed-frequency applications where programmability and ultra-low jitter are not required

Compared with Si5338A-B06163-GM, SI5338C-B06163-GMR provides identical hardware but distinct factory NVM settings; versus ICS8430I-01T, it adds full I²C programmability, 0.7 ps RMS jitter, and per-output phase/frequency agility - critical for next-gen serial interface timing.

Availability

SI5338C-B06163-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, broadcast video sync, and MSAN/DSLAM system clock tree applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B06163-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple fixed-frequency oscillators with a single configurable IC.

FAQ

What is the primary function of the SI5338C-B06163-GMR?

The SI5338C-B06163-GMR is an I²C-programmable quad clock generator IC that synthesizes four independent, low-jitter output clocks from a single reference input. Its core function is replacing up to four discrete crystal oscillators in high-speed digital systems such as PCIe switches, Ethernet PHYs, and FPGA-based video equipment while maintaining sub-picosecond jitter performance.

Does the SI5338C-B06163-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338C-B06163-GMR meets PCIe Gen 4 common clock specifications with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured with a 2–5 MHz PLL bandwidth and CDR = 10 MHz, as validated in Skyworks' AN562 and measured using the Skyworks PCIe Clock Jitter Tool. It is explicitly listed as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in the official datasheet.

How many input reference sources does the SI5338C-B06163-GMR accept?

The SI5338C-B06163-GMR accepts six configurable input sources: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz signals, two single-ended pins (IN3, IN4) supporting CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and an integrated 8–30 MHz crystal oscillator circuit. All inputs are selectable via register configuration.

Can the SI5338C-B06163-GMR generate different output voltage levels simultaneously?

Yes, the SI5338C-B06163-GMR supports independent output supply voltages per driver: VDDO0 through VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous LVDS (1.8 V), HCSL (3.3 V), and CMOS (2.5 V) outputs on the same device - eliminating external level shifters in mixed-voltage SoC/FPGA designs.

Is ClockBuilder Pro software required to configure the SI5338C-B06163-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338C-B06163-GMR configuration. The device supports full I²C/SMBus register access for manual programming; however, ClockBuilder Pro automates complex MultiSynth™ calculations, validates jitter performance, generates initialization scripts, and exports configuration files - significantly reducing development time and risk of misconfiguration.

SI5338C-B06163-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B06163-GMR FAQ

1.How can I place an order for SI5338C-B06163-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B06163-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B06163-GMR reliable?

The price and inventory of SI5338C-B06163-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B06163-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B06163-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B06163-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B06163-GMR?

SI5338C-B06163-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B06163-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B06163-GMR?

For technical support, including SI5338C-B06163-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B06163-GMR requirements.

6.How does Aetrix verify that SI5338C-B06163-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B06163-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B06163-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B06163-GMR?

All SI5338C-B06163-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B06163-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B06163-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B06163-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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