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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B10104-GM

Name: SI5338C-B10104-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B10104-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B10104-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338C-B10104-GM.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B10104-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338C-B10104-GM datasheet, SI5338C-B10104-GM pinout, SI5338C-B10104-GM application, or SI5338C-B10104-GM equivalent, this page delivers verified specifications, validated pin functions, real-world timing use cases, and two confirmed alternative parts for frequency synthesis, jitter-critical clock distribution, and multi-format output design.

Technical Context

The SI5338C-B10104-GM integrates a high-stability PLL with patented MultiSynth™ fractional-N synthesis per output channel, enabling independent any-frequency generation (0.16–710 MHz) with true zero-ppm accuracy. Its dual-stage synthesis architecture supports integer and fractional modes, external feedback for zero-delay operation, and programmable loop bandwidth (1.6 MHz typical).

It features full I²C/SMBus configuration of input references (crystal, CMOS, SSTL/HSTL, differential), output formats (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), supply voltages (1.5–3.3 V per driver), and advanced timing controls including ±45 ns programmable phase offset, 20 ps step resolution, and independent frequency increment/decrement at 1 ppm steps.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL formats
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 Common Clock requirements
Frequency Range	0.16–710 MHz per output; up to two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Operating Temperature	–40 to +85 °C, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B10104-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each configurable for format, voltage, and termination
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise timing operation
SCL, SDA	I²C interface	Standard SMBus-compatible serial bus (up to 400 kHz); supports in-system programming and status reads
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock (LOL) and loss-of-signal (LOS) conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with 0 ppm precision on all four outputs
PCIe Gen 1–4 compliance	Meets Common Clock jitter limits (0.11–0.45 ps RMS) and Gen 3 SRNS requirements without external filtering
Programmable phase offset	±45 ns range with <20 ps step resolution per output-critical for skew alignment in multi-lane SerDes
Spread spectrum control	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts
Glitchless frequency tuning	Independent 1 ppm-step increment/decrement via pin or I²C-enables dynamic clock scaling without output interruption

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clock Distribution
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched phase alignment. Use Value: Eliminates four discrete oscillators; achieves <10 ps output-to-output skew and 0.7 ps RMS jitter compliant with IEEE 802.3 and PCIe Base Spec 4.0.	Use Scenario: Server motherboard with multiple PCIe Gen 3/4 slots, CPU, and PCH requiring common-reference clocking with strict jitter budgets. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz common clock to root complex and endpoints, plus auxiliary clocks for SATA, USB, and management controllers. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter ≤0.45 ps, validated using Intel Clock Jitter Tool v1.6.4.
FPGA & Processor Clocking	Broadcast Video/Audio Timing
Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., transceiver refclk, logic fabric, DDR PHY, video subsystem). IC Role / Device Role / Timing Role: Configurable quad clock generator supplying LVDS/HCSL/LVPECL outputs at 100–710 MHz with independent voltage and format per bank. Use Value: Single-chip replacement for four oscillators; supports 1.8 V LVDS and 3.3 V CMOS simultaneously, simplifying power delivery and layout.	Use Scenario: SMPTE ST 2082 (12G-SDI) or AES67 audio-over-IP equipment requiring ultra-low-jitter 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks. IC Role / Device Role / Timing Role: Precision timing IC generating three synchronized broadcast-grade clocks with <0.7 ps RMS jitter and programmable phase offsets. Use Value: Enables frame-accurate synchronization across video encoders, decoders, and audio interfaces without external jitter cleaners.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clock Distribution

Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched phase alignment.

Use Value: Eliminates four discrete oscillators; achieves <10 ps output-to-output skew and 0.7 ps RMS jitter compliant with IEEE 802.3 and PCIe Base Spec 4.0.

Use Scenario: Server motherboard with multiple PCIe Gen 3/4 slots, CPU, and PCH requiring common-reference clocking with strict jitter budgets.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz common clock to root complex and endpoints, plus auxiliary clocks for SATA, USB, and management controllers.

Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter ≤0.45 ps, validated using Intel Clock Jitter Tool v1.6.4.

FPGA & Processor Clocking

Broadcast Video/Audio Timing

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., transceiver refclk, logic fabric, DDR PHY, video subsystem).

IC Role / Device Role / Timing Role: Configurable quad clock generator supplying LVDS/HCSL/LVPECL outputs at 100–710 MHz with independent voltage and format per bank.

Use Value: Single-chip replacement for four oscillators; supports 1.8 V LVDS and 3.3 V CMOS simultaneously, simplifying power delivery and layout.

Use Scenario: SMPTE ST 2082 (12G-SDI) or AES67 audio-over-IP equipment requiring ultra-low-jitter 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks.

IC Role / Device Role / Timing Role: Precision timing IC generating three synchronized broadcast-grade clocks with <0.7 ps RMS jitter and programmable phase offsets.

Use Value: Enables frame-accurate synchronization across video encoders, decoders, and audio interfaces without external jitter cleaners.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC clocking and high-channel-count data converters-not required for basic PCIe/FPGA clocking	Select when >4 outputs, sub-0.4 ps jitter, or deterministic delay control are mandatory
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis, no I²C, 0.9 ps RMS jitter	Limited to fanout-only roles; cannot generate arbitrary frequencies or replace crystals	Select only for simple clock distribution where input frequency matches all required outputs

Compared with Si5332A-D08189-GM, SI5338C-B10104-GM offers lower cost and simpler configuration for standard PCIe/FPGA applications, while ICS8430I-01T lacks synthesis capability entirely-making SI5338C-B10104-GM the only viable choice for any-frequency generation with jitter under 1 ps RMS.

Availability

SI5338C-B10104-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clock distribution, and FPGA & processor clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338C-B10104-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family is designed for high-performance, low-jitter clock generation in datacenter, telecom, and broadcast systems-enabling flexible, software-defined timing with minimal board space and power.

FAQ

What is the maximum output frequency supported by SI5338C-B10104-GM?

The SI5338C-B10104-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. All outputs maintain 0.7 ps RMS jitter within their rated ranges.

Does SI5338C-B10104-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B10104-GM meets PCIe Gen 4 Common Clock RMS jitter requirements (≤0.45 ps, 10 kHz–50 MHz) per Table 12 of the Skyworks Rev. 1.6 datasheet. It is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4, with 100 MHz HCSL outputs and PLL bandwidth set to 2–5 MHz.

Can SI5338C-B10104-GM generate different output voltages on each driver?

Yes, SI5338C-B10104-GM provides independent VDDO0–VDDO3 supplies, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components-e.g., 1.8 V LVDS FPGA inputs and 3.3 V CMOS microcontrollers-without level shifters.

How is SI5338C-B10104-GM programmed, and what tools are required?

SI5338C-B10104-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The tool auto-generates configuration files, validates jitter performance, and exports register maps for production programming. No external hardware programmer is needed-standard I²C host controller suffices.

What package type and thermal characteristics does SI5338C-B10104-GM have?

SI5338C-B10104-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, supporting reliable operation at full load across –40 to +85 °C ambient. Recommended PCB land pattern includes thermal vias under the exposed pad per Skyworks AN899.

SI5338C-B10104-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338C-B10104-GM FAQ

1.How can I place an order for SI5338C-B10104-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B10104-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B10104-GM reliable?

The price and inventory of SI5338C-B10104-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B10104-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B10104-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B10104-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B10104-GM?

SI5338C-B10104-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B10104-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B10104-GM?

For technical support, including SI5338C-B10104-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B10104-GM requirements.

6.How does Aetrix verify that SI5338C-B10104-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B10104-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B10104-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B10104-GM?

All SI5338C-B10104-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B10104-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B10104-GM part is unused and in its original packaging.

Return procedure for SI5338C-B10104-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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