Skyworks Solutions Inc. SI5338C-B10646-GM

Overview

SI5338C-B10646-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338C-B10646-GM datasheet, SI5338C-B10646-GM pinout, SI5338C-B10646-GM application, or SI5338C-B10646-GM equivalent, this device delivers any-frequency synthesis with ±1 ppm frequency accuracy, independent per-output voltage control (1.5/1.8/2.5/3.3 V), glitchless frequency adjustment in 1 ppm steps, and programmable phase offset <20 ps resolution - critical for SerDes alignment and multi-clock domain synchronization.

Technical Context

The SI5338C-B10646-GM implements a two-stage PLL architecture: a high-stability input stage with configurable reference inputs (crystal: 8–30 MHz; differential: 5–710 MHz) feeds a MultiSynth™ fractional-N synthesis engine that generates four independent output frequencies. Each output path includes dedicated R-, M-, and P-dividers enabling integer or fractional synthesis with <1 ppb resolution.

Its output stage supports mixed-signal configurations - up to four differential outputs (CLK0A/B through CLK3A/B), eight single-ended clocks, or combinations - with independent supply rails (VDDO0–VDDO3), spread spectrum modulation (0.5–5.0% down-spread, 33–63 kHz), loss-of-lock/loss-of-signal alarms, and pin-controlled frequency/phase increment/decrement for real-time tuning without I²C traffic.

Key Specifications

Pinout & Package

SI5338C-B10646-GM uses a 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family specification and include six input pins (IN1–IN6), eight output pins (CLK0A/B–CLK3A/B), four VDDO supplies (VDDO0–VDDO3), dual core VDD, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338C-B10646-GM, the Si5338A-B-GM offers identical flexibility at lower cost but omits Gen 4 timing certification, while the LMK04832 provides superior jitter cleaning at the expense of power, size, and complexity - making SI5338C-B10646-GM the optimal balance for PCIe Gen 4, FPGA, and telecom line card clocking where compactness, low power, and certified compliance are essential.

Availability

SI5338C-B10646-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, FPGA-based test equipment, and telecom line cards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338C-B10646-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in datacenter, networking, and broadcast systems - emphasizing low jitter, flexible format support, and software-configurable synthesis without external loop filters or VCXOs.

FAQ

What is the maximum output frequency supported by SI5338C-B10646-GM?

The SI5338C-B10646-GM supports up to 710 MHz on LVPECL/LVDS outputs, 350 MHz on HCSL, and 200 MHz on CMOS. For frequencies above 350 MHz, only two unique outputs may operate simultaneously - specifically Fvco/4 and Fvco/6 - as defined in the synthesis architecture. All outputs maintain 0.7 ps RMS typical jitter within their respective rated ranges.

Does SI5338C-B10646-GM support PCIe Gen 4 timing requirements?

Yes, SI5338C-B10646-GM is explicitly qualified for PCIe Gen 4 Common Clock mode with ≤0.45 ps RMS jitter (10 kHz–50 MHz), meeting PCI-SIG Base Specification 4.0 rev. 0.5. It also satisfies Gen 3 SRNS compliance and includes built-in jitter measurement support via Skyworks' PCIe Clock Jitter Tool.

Can SI5338C-B10646-GM generate different output voltages on each channel?

Yes, SI5338C-B10646-GM provides four independent VDDO supplies (VDDO0–VDDO3), allowing each output pair (CLK0, CLK1, CLK2, CLK3) to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices - e.g., 1.8 V FPGA I/O banks and 3.3 V legacy peripherals - without level shifters.

How is SI5338C-B10646-GM programmed in-system?

SI5338C-B10646-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration can be stored in on-chip OTP memory for autonomous startup, or dynamically updated during operation - including real-time frequency/phase adjustments using dedicated PINC/FINC and PDEC/FDEC control pins.

What reference inputs does SI5338C-B10646-GM accept?

SI5338C-B10646-GM accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz; two single-ended pins (IN3/IN4) for CMOS/SSTL/HSTL signals (5–350 MHz); and internal crystal oscillator support for 8–30 MHz crystals. All inputs feed into a configurable input stage with programmable termination and slew-rate monitoring.