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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B10646-GMR

Name: SI5338C-B10646-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B10646-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B10646-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338C-B10646-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338C-B10646-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats in a 4 × 4 mm 24-QFN package. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338C-B10646-GMR datasheet, SI5338C-B10646-GMR pinout, SI5338C-B10646-GMR application, or SI5338C-B10646-GMR equivalent, this page provides verified technical context, pin-level design meaning, PCIe- and Ethernet-specific jitter performance data, and validated alternative options for multi-clock system design.

Technical Context

The SI5338C-B10646-GMR implements a two-stage PLL architecture: a high-stability input stage locks to one of six configurable reference inputs (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers per output channel. Each synthesizer supports integer or fractional mode operation with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).

Its output stage features per-driver voltage selection (1.5/1.8/2.5/3.3 V), independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), glitchless frequency increment/decrement (1 ppm steps), and sub-20 ps phase adjustment granularity. Loss-of-lock and loss-of-signal alarms are provided via dedicated INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, SSTL, HSTL, or CMOS formats
Frequency range	0.16–710 MHz per output; up to two outputs >350 MHz simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), measured at 125 MHz output with 25 MHz reference; meets PCIe Gen 3 SRNS spec (≤0.32 ps RMS)
Input reference options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply & power	Core: 1.8/2.5/3.3 V ±10%; output buffers: 1.4–3.63 V; 45 mA typical core current at 100 MHz on all outputs
Operating temperature	–40 °C to +85 °C ambient; thermal resistance θJA = 37 °C/W (still air)
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B10646-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential reference inputs	Accept AC-coupled differential clocks (5–710 MHz); require external 100 Ω termination; slew rate >0.3 V/ns for optimal jitter
IN3, IN4	Single-ended reference inputs	Accept DC-coupled CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD; slew rate >1 V/ns recommended
CLK0A–CLK3B	Differential clock outputs	Four independent pairs; each pair supports format/voltage configuration; internal 22 Ω series resistor included
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage clock distribution without level shifters
VDD	Core supply	Single 1.8/2.5/3.3 V supply; PSRR optimized for noise immunity; 45 mA typical load at full output activity
SCL, SDA	I²C/SMBus interface	Standard-compliant 2-wire bus (up to 400 kHz); used for configuration, status readback, and real-time frequency tuning
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal; pulled up externally; 3 mA sink capability
GND, RSVD_GND	Ground connections	Multiple GND pins including reserved ground for noise isolation; thermal pad must be soldered to PCB ground plane

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm frequency accuracy on all outputs, with 1 ppb resolution
PCIe Gen 1–4 compliance	Validated total jitter ≤33.6 ps pk-pk (Gen 2) and ≤0.45 ps RMS (Gen 3/4 common clock), meeting Intel and PCI-SIG requirements
Per-output voltage & format control	Each output bank (VDDOx) independently set to 1.5/1.8/2.5/3.3 V; supports LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL, or CML
Glitchless frequency tuning	Hardware-supported frequency increment/decrement (1 ppm steps) and phase adjustment (<20 ps steps) without output interruption
Spread spectrum control	Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, enabling EMI reduction in dense PCB layouts
External feedback mode	Supports zero-delay operation by routing CLKOUT back to feedback input, eliminating propagation delay in synchronous systems

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized, low-jitter reference clocks to PCIe Gen 3/4 switches and endpoint devices in server and storage platforms. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Common Clock and SRNS specifications. Use Value: Enables deterministic link training and stable 8 GT/s data rates; eliminates need for four discrete oscillators and reduces board area by >60%.	Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE switch ASICs and PHYs. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing jitter-clean Ethernet reference clocks with programmable phase alignment across ports. Use Value: Meets IEEE 802.3 clause 49 jitter limits (≤0.7 ps RMS); supports multi-rate switching without hardware change.
Broadcast Video Synchronization	FPGA/Processor Clock Domain Crossing
Use Scenario: Distributing frame-locked timing signals across video encoders, decoders, and transport processors in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-phase-noise clock generator providing 27 MHz, 74.25 MHz, and 148.5 MHz SMPTE-compliant clocks with <20 ps inter-output skew. Use Value: Ensures pixel-accurate synchronization across multiple video pipelines; eliminates frame tearing and audio-video desync.	Use Scenario: Supplying independent, phase-aligned clocks to FPGA fabric, memory interfaces (DDR4), and CPU subsystems in embedded computing. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage domains (1.8 V DDR, 1.2 V core, 3.3 V I/O) with programmable phase offsets. Use Value: Simplifies clock tree design; enables precise setup/hold margin control and eliminates external delay lines or PLLs.

PCIe Gen 3/4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized, low-jitter reference clocks to PCIe Gen 3/4 switches and endpoint devices in server and storage platforms.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Common Clock and SRNS specifications.

Use Value: Enables deterministic link training and stable 8 GT/s data rates; eliminates need for four discrete oscillators and reduces board area by >60%.

Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE switch ASICs and PHYs.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing jitter-clean Ethernet reference clocks with programmable phase alignment across ports.

Use Value: Meets IEEE 802.3 clause 49 jitter limits (≤0.7 ps RMS); supports multi-rate switching without hardware change.

Broadcast Video Synchronization

FPGA/Processor Clock Domain Crossing

Use Scenario: Distributing frame-locked timing signals across video encoders, decoders, and transport processors in broadcast infrastructure.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator providing 27 MHz, 74.25 MHz, and 148.5 MHz SMPTE-compliant clocks with <20 ps inter-output skew.

Use Value: Ensures pixel-accurate synchronization across multiple video pipelines; eliminates frame tearing and audio-video desync.

Use Scenario: Supplying independent, phase-aligned clocks to FPGA fabric, memory interfaces (DDR4), and CPU subsystems in embedded computing.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage domains (1.8 V DDR, 1.2 V core, 3.3 V I/O) with programmable phase offsets.

Use Value: Simplifies clock tree design; enables precise setup/hold margin control and eliminates external delay lines or PLLs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same Si5338 family; differs in factory-programmed configuration (default output frequencies, I²C address, spread-spectrum settings)	No functional difference in PCIe/Ethernet timing; requires reprogramming via ClockBuilder Pro for identical behavior	Select when preconfigured startup behavior matches legacy designs; SI5338C-B10646-GMR offers optimized defaults for PCIe Gen 4 and 10 GbE.
LMK04832ISQE/NOPB	Two PLLs (not four independent synthesizers); higher power (120 mA typical); larger 7 × 7 mm package; supports JESD204B deterministic latency	Better suited for RF/data converter timing with sub-ps jitter; less flexible for multi-protocol, multi-frequency systems	Choose LMK04832 for JESD204B baseband timing; SI5338C-B10646-GMR is preferred for cost-sensitive, space-constrained PCIe/Ethernet applications.

Compared with Si5338A-B-GM, SI5338C-B10646-GMR provides factory-tuned defaults for PCIe Gen 4 and 10 GbE, reducing bring-up time; versus LMK04832, it delivers equivalent jitter at half the power and 40% smaller footprint, though without JESD204B deterministic latency support.

Availability

SI5338C-B10646-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE infrastructure, broadcast video synchronization, and FPGA-based embedded computing requiring stable component supply and long-term lifecycle support.

Supply support for SI5338C-B10646-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in high-performance RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-while maintaining ultra-low jitter and flexible output formatting.

FAQ

What is the default I²C address of the SI5338C-B10646-GMR?

The SI5338C-B10646-GMR has a factory-programmed I²C slave address of 0x70 (7-bit). This address is fixed and cannot be changed via hardware pins; configuration is performed exclusively through the SCL/SDA interface using Skyworks' ClockBuilder Pro software or custom firmware.

Does the SI5338C-B10646-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338C-B10646-GMR supports PCIe Gen 4 SRNS mode with ≤0.45 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–5 MHz and CDR = 10 MHz. This is validated per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed in Skyworks' AN562 application note.

Can the SI5338C-B10646-GMR generate three different frequencies above 350 MHz simultaneously?

No. The SI5338C-B10646-GMR can output only two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-as stated in Table 6 Note 6. Attempting a third >350 MHz output violates the VCO frequency constraints and will result in invalid synthesis.

What is the maximum output frequency for CMOS format on the SI5338C-B10646-GMR?

The SI5338C-B10646-GMR supports CMOS output frequencies up to 200 MHz. At 200 MHz, typical drive current is 13–18 mA (3.3 V VDDO), with rise/fall times of 0.45–0.85 ns into 2 pF load, as specified in Table 6.

Is external termination required for differential outputs of the SI5338C-B10646-GMR?

Yes. For LVDS, LVPECL, and HCSL outputs, external 100 Ω differential termination is required at the receiver end. The SI5338C-B10646-GMR includes internal 22 Ω series resistors per output leg, so no additional series termination is needed on the driver side.

SI5338C-B10646-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338C-B10646-GMR FAQ

1.How can I place an order for SI5338C-B10646-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B10646-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B10646-GMR reliable?

The price and inventory of SI5338C-B10646-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B10646-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B10646-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B10646-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B10646-GMR?

SI5338C-B10646-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B10646-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B10646-GMR?

For technical support, including SI5338C-B10646-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B10646-GMR requirements.

6.How does Aetrix verify that SI5338C-B10646-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B10646-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B10646-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B10646-GMR?

All SI5338C-B10646-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B10646-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B10646-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B10646-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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