Skyworks Solutions Inc. SI5338C-B10647-GMR

Overview

SI5338C-B10647-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338C-B10647-GMR datasheet, SI5338C-B10647-GMR pinout, SI5338C-B10647-GMR application, or SI5338C-B10647-GMR equivalent, this device delivers zero-ppm frequency accuracy per output, independent voltage control (1.5/1.8/2.5/3.3 V), glitchless 1-ppm frequency adjustment, and <20 ps phase step resolution - critical for PCIe, Ethernet, and FPGA clocking design validation.

Technical Context

The SI5338C-B10647-GMR implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2. Each output driver operates with its own M/N/R divider set and supports integer or fractional synthesis.

It features full I²C/SMBus programmability, loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and configurable spread-spectrum on any output (0.5–5.0% spread, 33–63 kHz modulation). Input reference flexibility includes 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential sources.

Key Specifications

Pinout & Package

SI5338C-B10647-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad (GND-connected). Pin assignments are fixed per Skyworks Si5338 family layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B-GM, SI5338C-B10647-GMR offers updated PCIe Gen 4 jitter compliance and broader input reference support; versus LMK04832ISQE/NOPB, it trades output count and ultimate jitter performance for smaller size, lower power, and simpler configuration - ideal for space-constrained networking and compute platforms.

Availability

SI5338C-B10647-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE switch clocking, and FPGA reference clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B10647-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces - designed specifically for PCIe, Ethernet, Fibre Channel, and broadcast video timing where precision, flexibility, and small footprint are critical.

FAQ

What is the default factory configuration of SI5338C-B10647-GMR?

The SI5338C-B10647-GMR ships with one-time-programmable (OTP) NVM preloaded with a customer-specific configuration defined during ordering. Unlike blank variants, this part boots directly into its designated output frequencies, formats, and voltages without requiring I²C initialization - reducing system boot time and firmware complexity. The exact configuration is documented in the Skyworks order-specific programming file delivered with the part.

Does SI5338C-B10647-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338C-B10647-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), meeting PCI-SIG Base Specification 4.0 rev 0.5 requirements. This is achieved using a 2–5 MHz PLL loop bandwidth and 10 MHz CDR reference, with output configured as HCSL at 100 MHz. The device's independent MultiSynth™ stages allow simultaneous SRNS-compliant outputs alongside other non-PCIe clocks.

Can SI5338C-B10647-GMR generate three different frequencies above 350 MHz simultaneously?

No. SI5338C-B10647-GMR can output only two unique frequencies above 350 MHz at once - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints and internal divider architecture. Attempting to configure three >350 MHz outputs will result in invalid synthesis or failure to lock. For designs requiring >2 high-frequency outputs, use multiple devices or select a higher-VCO alternative like Si5341.

What is the maximum allowable input slew rate for differential clock signals on SI5338C-B10647-GMR?

The SI5338C-B10647-GMR requires a minimum differential input slew rate of >0.3 V/ns on pins IN1/IN2 and IN5/IN6 for optimal jitter performance. Exceeding 1.0 V/ns is recommended to maintain <0.7 ps RMS phase jitter. Slew rates below 0.3 V/ns increase deterministic jitter and may trigger false loss-of-signal alarms. Measured at 20–80% crossing with 100 Ω termination.

How does the RSVD_GND pin affect thermal performance of SI5338C-B10647-GMR?

The RSVD_GND pin on SI5338C-B10647-GMR is internally connected to the exposed thermal pad and must be soldered to a solid GND plane per Skyworks PCB land pattern guidelines. Omitting this connection increases junction-to-ambient thermal resistance by ≥8 °C/W, risking thermal throttling above 60 °C ambient. Proper connection maintains the specified θJA of 37 °C/W and ensures reliable operation at full load across –40 to +85 °C.