Skyworks Solutions Inc. SI5338C-B11788-GM
- Part No.:
- SI5338C-B11788-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338C-B11788-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338C-B11788-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces multiple crystal oscillators in high-speed serial interface timing.
For engineers reviewing the SI5338C-B11788-GM datasheet, SI5338C-B11788-GM pinout, SI5338C-B11788-GM application, or SI5338C-B11788-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage configuration (1.5–3.3 V), 1 ppm step frequency increment/decrement, <20 ps phase adjustment resolution, and support for external crystal (8–30 MHz) or wide-range differential inputs (5–710 MHz).
Technical Context
The SI5338C-B11788-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output path includes programmable dividers (R, M, P), configurable output drivers, and dedicated voltage supplies (VDDO0–VDDO3) enabling mixed-signal format generation on a single die.
It supports both free-running synthesis and synchronous frequency translation modes, with loss-of-lock and loss-of-signal monitoring, external feedback for zero-delay operation, and spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output. The device integrates one-time-programmable (OTP) NVM for factory or field configuration storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz) |
| Input Reference Support | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Voltage Per Driver | Independently configurable to 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enables mixed-logic-level clock distribution |
| Frequency Adjustment Resolution | 1 ppm steps via pin control or I²C; enables glitchless real-time tuning without interrupting output |
| Phase Adjustment Resolution | <20 ps steps per output; supports precise skew alignment across multi-lane interfaces like PCIe or DDR |
| Supply Voltages | Core: 1.8 V / 2.5 V / 3.3 V (±10%); Output buffers: 1.4–3.63 V - simplifies power domain partitioning |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial and telecom line-card environments |
Pinout & Package
SI5338C-B11788-GM is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 24-QFN layout (Rev. 1.6, page 37), including six input pins (IN1–IN6), eight clock outputs (CLK0A/B through CLK3A/B), four VDDO supplies, dual VDD core rails, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); tolerate –0.1 V to VDD+0.1 V |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent pairs; each configurable as LVPECL, LVDS, HCSL, or CML with per-driver VDDO |
| VDDO0–VDDO3 | Output buffer supplies | Enable independent voltage setting per output pair - critical for mixed-interface systems |
| SCL/SDA | I²C configuration interface | Standard SMBus-compatible 1.8/2.5/3.3 V interface; supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Generates four independent, zero-ppm-accuracy clocks from a single reference - eliminates need for multiple XO/VCXO components |
| PCIe Gen 1–4 & SRNS Compliance | Validated 0.11–0.45 ps RMS jitter performance enables drop-in use in PCIe root complexes, switches, and endpoint designs |
| Independent Output Voltage Control | Each of four output banks powered separately (1.5/1.8/2.5/3.3 V) - supports simultaneous interfacing to FPGAs, ASICs, and SerDes with differing I/O standards |
| Glitchless Frequency Tuning | 1 ppm-step frequency increment/decrement via dedicated pins or I²C - maintains continuous clock output during dynamic rate adaptation |
| Programmable Spread Spectrum | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI without altering system timing margins |
| External Feedback Mode | Enables zero-delay clock buffering with sub-nanosecond propagation delay - ideal for clock forwarding applications |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Synchronization |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ports with strict jitter budget. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter clocks meeting PCIe Gen 4 Common Clock spec (0.15–0.45 ps RMS). Use Value: Eliminates four discrete oscillators while maintaining sub-0.5 ps RMS jitter margin and enabling per-port skew calibration via programmable phase offset. |
Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 1/10 GbE PHYs and packet processors in a modular Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing integer-related frequencies from a common 25 MHz crystal reference. Use Value: Reduces BOM count and PCB area versus multiple XOs; independent VDDO per output supports mixed 1.8 V PHY and 3.3 V control logic domains. |
| Broadcast Video Frame Sync | FPGA-Based Video Processing |
Use Scenario: Delivering genlock-capable 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) clocks with tight phase alignment across video processing modules. IC Role / Device Role / Timing Role: Precision clock generator with <20 ps phase step resolution and sub-100 ps output-to-output skew. Use Value: Enables frame-accurate synchronization across distributed video pipelines without external delay lines or manual trimming. |
Use Scenario: Supplying 200 MHz system clock, 100 MHz DDR3 interface clock, and 250 MHz transceiver reference to a high-end FPGA in broadcast infrastructure. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed CMOS, LVDS, and HCSL outputs from a single 25 MHz crystal. Use Value: Simplifies timing architecture by consolidating three clock domains into one IC with independent voltage and format control per output. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D09189-GM | Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs, supports JESD204B deterministic latency | Targets JESD204B-compliant data converters and multi-gigabit ADC/DAC systems where deterministic delay matters | Choose when >4 outputs, ultra-low jitter, or JESD204B sync is required; higher cost and larger 5×5 mm package |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis capability; 0.4 ps RMS jitter | Used only in fixed-clock distribution scenarios (e.g., legacy backplanes), lacks frequency agility or format flexibility | Choose only for simple clock replication where frequency reconfiguration is unnecessary and cost is primary constraint |
Compared with SI5338C-B11788-GM, the Si5332A offers superior jitter and scalability but requires redesign for JESD204B or 8-output needs, while the ICS8430I sacrifices programmability for lower unit cost and simpler layout - making SI5338C-B11788-GM optimal for flexible, PCIe/Ethernet timing where field reconfiguration and mixed-voltage support are essential.
Availability
SI5338C-B11788-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE synchronization, and broadcast video frame sync applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338C-B11788-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 family is engineered for high-performance, multi-protocol clock generation in datacenter, telecom, and broadcast systems - delivering programmable precision timing with minimal footprint and power.
FAQ
What is the maximum output frequency supported by SI5338C-B11788-GM in LVPECL mode?
The SI5338C-B11788-GM supports up to 710 MHz in LVPECL output mode, as specified in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10 GbE applications without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints.
Does SI5338C-B11788-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?
Yes, SI5338C-B11788-GM is explicitly validated for PCIe Gen 4 SRNS compliance with 0.11–0.32 ps RMS jitter (Table 12), measured under PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This makes SI5338C-B11788-GM suitable for root complex and endpoint designs requiring separate reference architecture.
Can SI5338C-B11788-GM generate different output voltages on each of its four output banks?
Yes, SI5338C-B11788-GM provides independent VDDO0–VDDO3 supplies, allowing each output bank to be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous driving of mixed-logic devices - for example, 1.8 V FPGA I/O, 2.5 V SerDes, and 3.3 V control logic - without level-shifting circuitry.
How is SI5338C-B11788-GM programmed, and is external non-volatile memory required?
SI5338C-B11788-GM is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software. It contains on-chip one-time-programmable (OTP) memory, so no external EEPROM or flash is needed for factory or field configuration storage. Configuration persists after power cycle.
What is the minimum input crystal frequency supported by SI5338C-B11788-GM?
The SI5338C-B11788-GM supports external crystals from 8 MHz to 30 MHz, as confirmed in Tables 8–11 of the datasheet. Crystals below 8 MHz are not supported; for lower-frequency references, users must apply CMOS, SSTL, or differential input signals (minimum 5 MHz).
SI5338C-B11788-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- PLL:
- Yes with Bypass
- Main Purpose:
- Ethernet, Fibre Channel, PCI Express (PCIe), Telecom
- Input:
- CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal
- Output:
- CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 3:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 200MHz
- Voltage - Supply:
- 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338C-B11788-GM FAQ
1.How can I place an order for SI5338C-B11788-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338C-B11788-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338C-B11788-GM reliable?
The price and inventory of SI5338C-B11788-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B11788-GM is usually 5 days.
3.What payment methods are accepted for SI5338C-B11788-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B11788-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338C-B11788-GM?
SI5338C-B11788-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338C-B11788-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338C-B11788-GM?
For technical support, including SI5338C-B11788-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B11788-GM requirements.
6.How does Aetrix verify that SI5338C-B11788-GM is sourced from the original manufacturer or authorized distributors?
All SI5338C-B11788-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B11788-GM meets industry standards.
7.What is the process for return or replacement of SI5338C-B11788-GM?
All SI5338C-B11788-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B11788-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338C-B11788-GM part is unused and in its original packaging.
Return procedure for SI5338C-B11788-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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