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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B11788-GMR

Name: SI5338C-B11788-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B11788-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338C-B11788-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B11788-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338C-B11788-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338C-B11788-GMR datasheet, SI5338C-B11788-GMR pinout, SI5338C-B11788-GMR application, or SI5338C-B11788-GMR equivalent, key selection factors include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN 4×4 mm package with I²C/SMBus interface.

Technical Context

The SI5338C-B11788-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), 20 ps step resolution for phase increment/decrement, and frequency adjustment in 1 ppm steps.

It supports flexible input configurations-including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz)-and delivers output formats including LVPECL, LVDS, HCSL, CML, CMOS, SSTL, and HSTL. Output drivers are individually powered (VDDO0–VDDO3), enabling mixed-voltage system clock distribution without level shifters.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports simultaneous dual >350 MHz outputs (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Format Flexibility	LVPECL/LVDS/HCSL/CML/CMOS/SSTL/HSTL per driver; independent VDDO (1.5/1.8/2.5/3.3 V)
Supply Voltage	VDD core: 1.8/2.5/3.3 V ± tolerance; VDDO: 1.4–3.63 V; 45 mA typ core current at 100 MHz on all outputs
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management

Pinout & Package

SI5338C-B11788-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 1/2), IN5/IN6 (differential ref 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL; IN3 = primary, IN4 = secondary; 5–350 MHz range
IN5 / IN6	Differential reference inputs 2 & 3	Enable multi-reference redundancy or frequency translation; same specs as IN1/IN2
CLK0A / CLK0B	Differential output 0 pair	Configurable format (LVPECL/LVDS/HCSL/etc.); driven by MultiSynth 0; VDDO0 referenced
CLK1A / CLK1B	Differential output 1 pair	Independent of CLK0; supports same formats and frequencies; VDDO1 referenced
CLK2A / CLK2B	Differential output 2 pair	Third independent output; full frequency/format configurability; VDDO2 referenced
CLK3A / CLK3B	Differential output 3 pair	Fourth output; enables true quad-clock generation with zero ppm accuracy per channel
VDDO0–VDDO3	Output buffer supply pins	Allow per-output voltage setting (1.5/1.8/2.5/3.3 V); enable mixed-signal SoC interfacing
VDD	Core supply	1.8/2.5/3.3 V core power; PSRR optimized for clean clock synthesis
SCL / SDA	I²C/SMBus interface	Standard two-wire serial programming; supports ClockBuilder Pro configuration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events
RSVD_GND	Reserved ground	Internal no-connect; recommended to tie to PCB ground plane for EMI control

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers deliver 0 ppm precision across 0.16–710 MHz per output
PCIe Gen 1–4 Compliance	Meets Common Clock jitter specs (Gen 1–4) and Gen 3 SRNS; validated with Intel Clock Jitter Tool
Independent Output Voltage Control	VDDO0–VDDO3 allow per-output 1.5/1.8/2.5/3.3 V supply-eliminates external level shifters in mixed-voltage systems
Programmable Spread Spectrum	Per-output SSC: 0.5–5.0% down-spread, 33–63 kHz modulation rate; reduces EMI in dense PCB layouts
Glitchless Frequency Adjustment	1 ppm step size via PINC/FDEC pins; update time <667 ns for outputs >18 MHz-enables dynamic frequency scaling
Phase Adjustment Resolution	<20 ps step accuracy with ±45 ns range per output; supports precise skew alignment in SerDes timing paths

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clock Distribution
Use Scenario: High-density 1/10 GbE switching fabric requiring low-jitter, multi-frequency clocks for MAC, PHY, and packet processor subsystems. IC Role / Device Role / Timing Role: Quad clock generator providing independent 125 MHz (GbE), 156.25 MHz (10GbE), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-1 ps RMS jitter. Use Value: Replaces four discrete oscillators; eliminates board-level skew between domains; meets IEEE 802.3 and PCI-SIG jitter masks without external cleanup.	Use Scenario: Server motherboard with multiple PCIe Gen 3/4 slots and CPU/U.2 NVMe controllers needing synchronized, low-phase-noise reference clocks. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz HCSL to all PCIe endpoints while meeting Gen 4 SRNS jitter spec (≤0.45 ps RMS). Use Value: Single-device solution avoids timing loop risks of daisy-chained buffers; supports spread spectrum on non-critical outputs to reduce system EMI.
FPGA & Processor Clocking	Broadcast Video/Audio Timing
Use Scenario: Heterogeneous compute platform with Xilinx Versal FPGA, ARM-based SoC, DDR4 memory, and PCIe peripherals-all requiring distinct, phase-aligned clocks. IC Role / Device Role / Timing Role: Configurable clock hub generating 300 MHz (FPGA logic), 1 GHz (ARM core), 1.2 GHz (DDR4), and 100 MHz (PCIe) from one crystal reference. Use Value: Eliminates need for multiple crystal oscillators and discrete fanout buffers; enables dynamic reconfiguration via I²C during runtime.	Use Scenario: SMPTE ST 2110 IP video router requiring SMPTE 2059-2 PTP synchronization, 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and AES audio clocks (48/96 kHz). IC Role / Device Role / Timing Role: Precision timing engine delivering ultra-low-jitter outputs traceable to GPS-disciplined reference via IN3/IN4. Use Value: Meets broadcast-grade jitter requirements (<0.5 ps RMS for SDI); supports independent phase alignment across video/audio domains.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clock Distribution

Use Scenario: High-density 1/10 GbE switching fabric requiring low-jitter, multi-frequency clocks for MAC, PHY, and packet processor subsystems.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 125 MHz (GbE), 156.25 MHz (10GbE), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-1 ps RMS jitter.

Use Value: Replaces four discrete oscillators; eliminates board-level skew between domains; meets IEEE 802.3 and PCI-SIG jitter masks without external cleanup.

Use Scenario: Server motherboard with multiple PCIe Gen 3/4 slots and CPU/U.2 NVMe controllers needing synchronized, low-phase-noise reference clocks.

IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz HCSL to all PCIe endpoints while meeting Gen 4 SRNS jitter spec (≤0.45 ps RMS).

Use Value: Single-device solution avoids timing loop risks of daisy-chained buffers; supports spread spectrum on non-critical outputs to reduce system EMI.

FPGA & Processor Clocking

Broadcast Video/Audio Timing

Use Scenario: Heterogeneous compute platform with Xilinx Versal FPGA, ARM-based SoC, DDR4 memory, and PCIe peripherals-all requiring distinct, phase-aligned clocks.

IC Role / Device Role / Timing Role: Configurable clock hub generating 300 MHz (FPGA logic), 1 GHz (ARM core), 1.2 GHz (DDR4), and 100 MHz (PCIe) from one crystal reference.

Use Value: Eliminates need for multiple crystal oscillators and discrete fanout buffers; enables dynamic reconfiguration via I²C during runtime.

Use Scenario: SMPTE ST 2110 IP video router requiring SMPTE 2059-2 PTP synchronization, 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and AES audio clocks (48/96 kHz).

IC Role / Device Role / Timing Role: Precision timing engine delivering ultra-low-jitter outputs traceable to GPS-disciplined reference via IN3/IN4.

Use Value: Meets broadcast-grade jitter requirements (<0.5 ps RMS for SDI); supports independent phase alignment across video/audio domains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08180-GM	Higher integration: includes integrated crystal; lower jitter (0.35 ps RMS); supports up to 10 outputs; 32-QFN package	Targeted at space-constrained, ultra-low-jitter designs (e.g., AI accelerators, 5G RU); lacks independent VDDO per output	Select when crystal integration and sub-0.4 ps jitter are critical; avoid if per-output voltage flexibility or legacy Si5338 footprint is required
ICS853S01AG-01LF	Fixed-function 4-output LVDS clock generator; no I²C programmability; 1.5 ps RMS jitter; 3.3 V only; 24-TSSOP	Cost-sensitive, static-clock applications (e.g., industrial PLCs); no frequency translation or spread spectrum	Select for simple, unchanging clock trees where programmability adds unnecessary complexity or cost

Compared with Si5332A-D08180-GM, SI5338C-B11788-GMR offers superior per-output voltage control and pin compatibility with existing Si5338 designs, while trading off some jitter performance and crystal integration. Against ICS853S01AG-01LF, it provides full field reprogrammability and multi-standard compliance at higher design flexibility cost.

Availability

SI5338C-B11788-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server platforms, and FPGA-based embedded systems requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature operation.

Supply support for SI5338C-B11788-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock innovation.

The SI5338C-B11788-GMR belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-density, multi-protocol systems requiring flexible, low-jitter clock synthesis in compact form factors.

FAQ

What is the maximum output frequency supported by SI5338C-B11788-GMR on a single channel?

The SI5338C-B11788-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as confirmed in Table 6 of the datasheet. This limit ensures VCO stability and jitter performance integrity across all four outputs.

Does SI5338C-B11788-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338C-B11788-GMR meets PCIe Gen 4 Common Clock RMS jitter requirements (≤0.45 ps RMS, 10 kHz–50 MHz) as verified in Table 12 of the datasheet. It achieves this using a 2–5 MHz PLL bandwidth and is validated with the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 under HCSL 100 MHz output conditions.

Can SI5338C-B11788-GMR generate different output voltages on each channel?

Yes, SI5338C-B11788-GMR provides independent output supply pins VDDO0 through VDDO3, each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices-e.g., 1.8 V FPGA I/O banks, 3.3 V legacy peripherals, and 2.5 V memory controllers-without external level shifters or voltage translators.

How is SI5338C-B11788-GMR programmed in-system?

SI5338C-B11788-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins). Configuration is typically performed using Skyworks' ClockBuilder Pro software, which generates register maps and .cmb files. The device also supports pin-controlled frequency/phase adjustments (PINC/FDEC) and interrupt-driven status monitoring (INTR pin) for real-time system control.

What reference inputs does SI5338C-B11788-GMR accept?

SI5338C-B11788-GMR accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz; two single-ended inputs (IN3, IN4) supporting CMOS/SSTL/HSTL at 5–350 MHz; and an on-chip oscillator for 8–30 MHz crystals. All inputs are selectable per MultiSynth stage, enabling redundant references or synchronous frequency translation.

SI5338C-B11788-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B11788-GMR FAQ

1.How can I place an order for SI5338C-B11788-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B11788-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B11788-GMR reliable?

The price and inventory of SI5338C-B11788-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B11788-GMR is usually 5 days.

3.What payment methods are accepted for SI5338C-B11788-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B11788-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B11788-GMR?

SI5338C-B11788-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B11788-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B11788-GMR?

For technical support, including SI5338C-B11788-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B11788-GMR requirements.

6.How does Aetrix verify that SI5338C-B11788-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338C-B11788-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B11788-GMR meets industry standards.

7.What is the process for return or replacement of SI5338C-B11788-GMR?

All SI5338C-B11788-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B11788-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B11788-GMR part is unused and in its original packaging.

Return procedure for SI5338C-B11788-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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