Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338C-B12236-GM

Name: SI5338C-B12236-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B12236-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338C-B12236-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B12236-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,640

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338C-B12236-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, zero-ppm-accurate output clocks (0.16–710 MHz) in LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, each configurable for voltage (1.5–3.3 V), phase (<20 ps step), and spread spectrum. It supports PCIe Gen 1–4 common clock and SRNS compliance, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package.

For engineers reviewing the SI5338C-B12236-GM datasheet, SI5338C-B12236-GM pinout, SI5338C-B12236-GM application, or SI5338C-B12236-GM equivalent, key selection criteria include differential output jitter (0.7 ps RMS typ), flexible input support (crystal, CMOS, SSTL, differential up to 710 MHz), independent frequency increment/decrement (1 ppm steps), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338C-B12236-GM implements a two-stage PLL architecture: a high-stability reference stage (input conditioning and R-divider) followed by four independent MultiSynth™ synthesis blocks (M0–M3), each feeding a configurable output driver. Each MultiSynth supports fractional-N synthesis with <1 ppb resolution and enables true zero-ppm output accuracy regardless of input reference stability.

Its output stage provides per-driver supply voltage selection (VDDO0–VDDO3), independent format configuration (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), and hardware-controlled features including glitchless frequency stepping (via FINC/FDEC pins), programmable phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% down-spread, 33–63 kHz).

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential outputs (CLK0A/B through CLK3A/B); supports up to 8 single-ended or mixed configurations
Frequency range per output	0.16–710 MHz (LVPECL/LVDS/CML), 0.16–350 MHz (SSTL/HSTL), 0.16–250 MHz (HCSL), 0.16–200 MHz (CMOS)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 common clock specs
Input reference support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Operating temperature	–40 °C to +85 °C, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338C-B12236-GM is housed in a 24-lead, 4 × 4 mm QFN package with wettable flank leads and an exposed thermal pad (GND-connected). Pin 1 is top-left corner (IN1), with clockwise numbering; pin 24 is bottom-left (GND). The package supports reflow per JEDEC J-STD-020 and achieves θ_JA = 37 °C/W in still air.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled differential references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair (e.g., CLK0A/CLK0B) delivers complementary signals
VDDO0–VDDO3	Output buffer supplies	Independent power rails per output bank; set voltage level and drive strength for each format
VDD	Core supply	1.8/2.5/3.3 V core logic supply; PSRR optimized for low-noise timing operation
SCL, SDA	I²C/SMBus interface	Standard two-wire serial bus (up to 400 kHz) for register programming and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation with <1 ppb resolution and zero ppm accuracy
PCIe Gen 4 compliance	Meets Common Clock jitter spec (0.15–0.45 ps RMS) and Gen 3 SRNS requirements without external filtering
Glitchless frequency tuning	Hardware-supported FINC/FDEC pins allow real-time, sub-ppm frequency adjustment (1 ppm steps) without output interruption
Per-output voltage & format control	Each of four output banks supports independent VDDO (1.5–3.3 V) and signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL)
Programmable spread spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts
Low-power operation	45 mA typical core current at 100 MHz on all outputs; <12 mA in buffer-only (PLL bypass) mode

Applications

Ethernet Switch/Routing	PCIe Gen 1–4 Timing
Use Scenario: High-density 1/10 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Primary clock source generating four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) for SERDES lanes and system logic. Use Value: Eliminates need for four discrete oscillators while maintaining PCIe Gen 4-compliant jitter (<0.45 ps RMS) and enabling dynamic frequency scaling via I²C.	Use Scenario: Server motherboard or add-in card implementing PCIe Gen 3/4 root complex or endpoint with strict common-clock jitter limits. IC Role / Device Role / Timing Role: Common clock generator delivering 100 MHz HCSL clocks to multiple slots with SRNS compliance and deterministic skew control. Use Value: Achieves 0.11–0.32 ps RMS jitter in SRNS mode and supports hardware-based frequency margining for validation testing.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: SMPTE ST 2082/2081 video router or frame synchronizer needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase alignment. IC Role / Device Role / Timing Role: Multi-format clock synthesizer providing LVDS and HCSL outputs simultaneously to video encoders, decoders, and serializers. Use Value: Independent phase adjustment (<20 ps step) and zero-ppm synthesis ensure frame-accurate genlock across distributed video processing paths.	Use Scenario: Industrial FPGA-based controller requiring separate clocks for DDR3/4 memory interface (e.g., 400 MHz), logic fabric (e.g., 200 MHz), and peripheral buses (e.g., 50 MHz). IC Role / Device Role / Timing Role: Configurable clock hub supplying CMOS, SSTL, and LVDS outputs with independent voltage rails matching each subsystem's I/O standard. Use Value: Reduces BOM count and layout complexity while supporting dynamic voltage/frequency scaling via I²C register writes during runtime.

Ethernet Switch/Routing

PCIe Gen 1–4 Timing

Use Scenario: High-density 1/10 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Primary clock source generating four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) for SERDES lanes and system logic.

Use Value: Eliminates need for four discrete oscillators while maintaining PCIe Gen 4-compliant jitter (<0.45 ps RMS) and enabling dynamic frequency scaling via I²C.

Use Scenario: Server motherboard or add-in card implementing PCIe Gen 3/4 root complex or endpoint with strict common-clock jitter limits.

IC Role / Device Role / Timing Role: Common clock generator delivering 100 MHz HCSL clocks to multiple slots with SRNS compliance and deterministic skew control.

Use Value: Achieves 0.11–0.32 ps RMS jitter in SRNS mode and supports hardware-based frequency margining for validation testing.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: SMPTE ST 2082/2081 video router or frame synchronizer needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase alignment.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer providing LVDS and HCSL outputs simultaneously to video encoders, decoders, and serializers.

Use Value: Independent phase adjustment (<20 ps step) and zero-ppm synthesis ensure frame-accurate genlock across distributed video processing paths.

Use Scenario: Industrial FPGA-based controller requiring separate clocks for DDR3/4 memory interface (e.g., 400 MHz), logic fabric (e.g., 200 MHz), and peripheral buses (e.g., 50 MHz).

IC Role / Device Role / Timing Role: Configurable clock hub supplying CMOS, SSTL, and LVDS outputs with independent voltage rails matching each subsystem's I/O standard.

Use Value: Reduces BOM count and layout complexity while supporting dynamic voltage/frequency scaling via I²C register writes during runtime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs; requires different programming flow	Targeted at space-constrained designs where crystal footprint reduction and ultra-low jitter are critical	Choose when board area is constrained and jitter budget is tighter than 0.7 ps RMS; verify ClockBuilder Pro compatibility for existing firmware
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface or frequency flexibility	Used in cost-sensitive, static-clocking applications where only one fixed frequency set is needed	Choose only if design requires no field reconfiguration and uses exclusively LVDS outputs at pre-defined frequencies (e.g., 100/125/156.25 MHz)

Compared with Si5332A-D08189-GM, SI5338C-B12236-GM offers broader input flexibility (external crystal or clock) and simpler I²C register mapping, while ICS8430I-01T lacks programmability entirely-making SI5338C-B12236-GM the optimal balance of configurability, jitter performance, and ease of integration for multi-standard systems.

Availability

SI5338C-B12236-GM is available at Aetrix Electronics and suitable for Ethernet switching, PCIe Gen 4 add-in cards, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338C-B12236-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 family was designed to replace multiple discrete oscillators in high-speed digital systems, delivering programmable, low-jitter clock synthesis for PCIe, Ethernet, and broadcast video applications with minimal board space and design effort.

FAQ

What input reference types does the SI5338C-B12236-GM support?

The SI5338C-B12236-GM accepts four input reference types: external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), single-ended SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). Differential inputs require external 100 Ω termination. All inputs feed into a programmable R-divider before the PLL stage, enabling wide-ranging reference compatibility without external circuitry. SI5338C-B12236-GM supports automatic loss-of-signal detection on all input types.

Does the SI5338C-B12236-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338C-B12236-GM meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS, 10 kHz–50 MHz) when configured with appropriate PLL bandwidth (2–4 MHz or 2–5 MHz) and CDR settings. It also satisfies PCIe Gen 3 Separate Reference No Spread (SRNS) requirements (0.11–0.32 ps RMS) and is validated using the Skyworks PCIe Clock Jitter Tool. SI5338C-B12236-GM achieves this with HCSL 100 MHz outputs and internal jitter optimization.

How many independent output voltage supplies does the SI5338C-B12236-GM provide?

The SI5338C-B12236-GM provides four independent output buffer supply rails: VDDO0, VDDO1, VDDO2, and VDDO3. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V to match the I/O voltage of the connected device (e.g., FPGA bank, ASIC, or PHY). This allows mixed-signal interfacing-such as LVDS at 2.5 V and CMOS at 1.8 V-without level shifters. SI5338C-B12236-GM maintains specified jitter performance across all supported VDDO combinations.

Can the SI5338C-B12236-GM generate frequencies above 350 MHz on all four outputs simultaneously?

No. While the SI5338C-B12236-GM supports up to 710 MHz on individual outputs, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-due to VCO frequency constraints and MultiSynth division limitations. Outputs above 350 MHz must share these two VCO-derived frequencies. SI5338C-B12236-GM documentation explicitly restricts simultaneous >350 MHz outputs to two distinct values, regardless of output format or pin assignment.

Is ClockBuilder Pro software required to configure the SI5338C-B12236-GM?

ClockBuilder Pro is not required but strongly recommended for initial configuration and validation of the SI5338C-B12236-GM. It auto-generates I²C register maps, validates frequency plans, and exports configuration files for production programming. SI5338C-B12236-GM can be programmed directly via I²C using custom firmware, but ClockBuilder Pro ensures correct register sequencing, jitter optimization, and compliance with PCIe/Ethernet timing standards.

SI5338C-B12236-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: Yes with Bypass

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B12236-GM FAQ

1.How can I place an order for SI5338C-B12236-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B12236-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B12236-GM reliable?

The price and inventory of SI5338C-B12236-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B12236-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B12236-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B12236-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B12236-GM?

SI5338C-B12236-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B12236-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B12236-GM?

For technical support, including SI5338C-B12236-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B12236-GM requirements.

6.How does Aetrix verify that SI5338C-B12236-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B12236-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B12236-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B12236-GM?

All SI5338C-B12236-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B12236-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B12236-GM part is unused and in its original packaging.

Return procedure for SI5338C-B12236-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…