Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5338C-B15672-GM

Name: SI5338C-B15672-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338C-B15672-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338C-B15672-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338C-B15672-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,555

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338C-B15672-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and PCIe timing systems.

For engineers reviewing the SI5338C-B15672-GM datasheet, SI5338C-B15672-GM pinout, SI5338C-B15672-GM application, or SI5338C-B15672-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control (0.5–5.0% at 33–63 kHz), and glitchless frequency adjustment in 1 ppm steps.

Technical Context

The SI5338C-B15672-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its core uses a single 1.8/2.5/3.3 V supply with >60 dB PSRR.

Each output supports independent format selection, voltage setting, phase offset (±45 ns in <20 ps steps), and spread-spectrum modulation. Input references include external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clocks (5–710 MHz), enabling direct replacement of legacy oscillators without board redesign.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements with low deterministic jitter contribution
Output Frequency Range	0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system clock tree design
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage interface with FPGAs, ASICs, and SerDes
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for high-density PCB layouts with thermal pad for 10 °C/W θJC
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Core Supply Current	45 mA typ at 100 MHz on all outputs - enables low-power timing in always-on subsystems

Pinout & Package

SI5338C-B15672-GM is housed in a thermally enhanced 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx supplies (VDDO0–VDDO3), dual core VDD pins, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz with independent VDDO0 voltage
CLK1A / CLK1B	Differential Output Pair 1	Independent format/voltage/frequency control; phase adjustable in <20 ps steps
CLK2A / CLK2B	Differential Output Pair 2	Supports spread-spectrum modulation (0.5–5.0%, 33–63 kHz); zero-delay mode via external feedback
CLK3A / CLK3B	Differential Output Pair 3	Glitchless frequency increment/decrement via PINC/FDEC pins in 1 ppm steps
IN1 / IN2, IN5 / IN6	Differential Reference Inputs	Accept 5–710 MHz AC-coupled signals; internal 10 kΩ termination; optimized for <0.3 V/ns slew rate
IN3 / IN4	Single-Ended Reference Inputs	Accept 5–200 MHz CMOS/SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD; 4 pF input capacitance
SCL / SDA	I²C/SMBus Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports ClockBuilder Pro programming
INTR	Interrupt Output	Open-drain status pin asserting loss-of-lock or loss-of-signal alarms; 3 mA sink capability
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V rails per output pair - enables mixed-interface clock distribution
VDD	Core Supply	Single 1.8/2.5/3.3 V supply; 45 mA typical current; >60 dB PSRR suppresses power rail noise

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy across 0.16–710 MHz without external VCXOs
PCIe Gen 1–4 Compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS) and supports Gen 4 CDR lock range
Per-Output Voltage & Format Control	Each of four output drivers configurable for LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL with dedicated 1.5/1.8/2.5/3.3 V VDDO rail
Glitchless Frequency Adjustment	PINC/FDEC pins enable real-time 1 ppm-step frequency tuning without output interruption or phase discontinuity
Programmable Phase Offset	±45 ns range in <20 ps resolution per output - enables precise skew management in multi-lane SerDes interfaces
Spread Spectrum Modulation	Configurable on any output: 0.5–5.0% down-spread at 33–63 kHz - reduces EMI peak emissions in dense PCB layouts

Applications

PCIe Gen 3/4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized reference clocks to multiple PCIe root complexes and endpoints in server backplanes and accelerators. IC Role / Device Role / Timing Role: Quad-output common clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Gen 3 SRNS and Gen 4 jitter limits. Use Value: Eliminates need for four discrete oscillators; achieves 0.11 ps RMS jitter at 100 MHz, meeting Intel's SRNS specification without external filtering.	Use Scenario: Generating multi-rate clocks for 1 GbE and 10 GbE PHYs, MACs, and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Configurable clock source providing 125 MHz (GbE), 156.25 MHz (10GbE), and 250 MHz (PHY interface) simultaneously from one device. Use Value: Reduces BOM count and layout area; supports dynamic reconfiguration via I²C during link training or speed negotiation.
FPGA/ASIC Clock Distribution	Broadcast Video Timing
Use Scenario: Delivering clean, low-jitter clocks to FPGA transceivers, memory controllers, and logic fabric in broadcast infrastructure and test equipment. IC Role / Device Role / Timing Role: Four-output generator supplying 148.5 MHz (SMPTE), 297 MHz (dual-link), 100 MHz (PCIe), and 50 MHz (control logic) with independent voltage and format settings. Use Value: Enables single-chip clock tree with sub-1 ps RMS jitter - preserves SERDES eye margin and DDR4 timing margins.	Use Scenario: Synchronizing frame-accurate timing across video encoders, decoders, and genlock systems in broadcast studios and OB vans. IC Role / Device Role / Timing Role: Precision clock generator producing SMPTE 2081-10-compliant 148.5 MHz, 297 MHz, and 594 MHz outputs with <20 ps inter-output skew. Use Value: Meets SMPTE ST 2081-10 phase stability requirements (<±1 ns over temperature); supports frame-locked multi-camera switching.

PCIe Gen 3/4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized reference clocks to multiple PCIe root complexes and endpoints in server backplanes and accelerators.

IC Role / Device Role / Timing Role: Quad-output common clock generator delivering four independent 100 MHz HCSL clocks compliant with PCIe Gen 3 SRNS and Gen 4 jitter limits.

Use Value: Eliminates need for four discrete oscillators; achieves 0.11 ps RMS jitter at 100 MHz, meeting Intel's SRNS specification without external filtering.

Use Scenario: Generating multi-rate clocks for 1 GbE and 10 GbE PHYs, MACs, and packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Configurable clock source providing 125 MHz (GbE), 156.25 MHz (10GbE), and 250 MHz (PHY interface) simultaneously from one device.

Use Value: Reduces BOM count and layout area; supports dynamic reconfiguration via I²C during link training or speed negotiation.

FPGA/ASIC Clock Distribution

Broadcast Video Timing

Use Scenario: Delivering clean, low-jitter clocks to FPGA transceivers, memory controllers, and logic fabric in broadcast infrastructure and test equipment.

IC Role / Device Role / Timing Role: Four-output generator supplying 148.5 MHz (SMPTE), 297 MHz (dual-link), 100 MHz (PCIe), and 50 MHz (control logic) with independent voltage and format settings.

Use Value: Enables single-chip clock tree with sub-1 ps RMS jitter - preserves SERDES eye margin and DDR4 timing margins.

Use Scenario: Synchronizing frame-accurate timing across video encoders, decoders, and genlock systems in broadcast studios and OB vans.

IC Role / Device Role / Timing Role: Precision clock generator producing SMPTE 2081-10-compliant 148.5 MHz, 297 MHz, and 594 MHz outputs with <20 ps inter-output skew.

Use Value: Meets SMPTE ST 2081-10 phase stability requirements (<±1 ns over temperature); supports frame-locked multi-camera switching.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B15672-GM	Same silicon die and pinout; differs only in factory-programmed NVM configuration - lacks pre-loaded B15672 frequency profile	Requires full ClockBuilder Pro configuration; not pre-programmed for 156.25 MHz reference and PCIe-compliant outputs	Select SI5338C-B15672-GM when drop-in replacement for existing 156.25 MHz PCIe timing designs is required without reprogramming.
ICS853S01AGI-01LFT	Fixed-frequency 156.25 MHz LVDS quad output; no I²C programmability, no spread spectrum, no voltage/format flexibility	Limited to single-frequency, single-format deployments; no support for PCIe SRNS or multi-standard clock trees	Choose ICS853S01AGI-01LFT only for cost-sensitive, static-clock applications where reprogrammability and jitter headroom are not required.

Compared with Si5338A-B15672-GM, the SI5338C-B15672-GM delivers immediate plug-and-play operation for PCIe Gen 3/4 systems; compared with ICS853S01AGI-01LFT, it provides field-upgradable frequency agility, lower jitter, and mixed-signal interface support - critical for next-generation programmable infrastructure.

Availability

SI5338C-B15672-GM is available at Aetrix Electronics and suitable for PCIe Gen 3/4 timing, Ethernet switch/router clocking, and FPGA/ASIC clock distribution requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338C-B15672-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock innovation.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in datacenter, telecom, and broadcast systems - emphasizing ultra-low jitter, software-defined frequency agility, and seamless integration with FPGAs, CPUs, and SerDes PHYs.

FAQ

What is the default factory configuration of the SI5338C-B15672-GM?

The SI5338C-B15672-GM ships with non-volatile memory (NVM) pre-programmed for a 156.25 MHz reference input and four PCIe Gen 3-compliant 100 MHz HCSL outputs. This eliminates the need for initial I²C programming in standard server and accelerator applications. The configuration is stored in one-time-programmable (OTP) memory and persists through power cycles. SI5338C-B15672-GM retains full ClockBuilder Pro reprogrammability if system requirements change.

Does the SI5338C-B15672-GM support PCIe Gen 4 Common Clock mode?

Yes, the SI5338C-B15672-GM meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. It achieves this using its 2–5 MHz PLL bandwidth setting and supports CDR lock ranges up to 100 ppm. The SI5338C-B15672-GM's 0.7 ps RMS typical phase jitter provides design margin beyond the Gen 4 requirement, ensuring robust operation under voltage and temperature variation.

Can the SI5338C-B15672-GM generate frequencies above 350 MHz on all four outputs simultaneously?

No. While the SI5338C-B15672-GM supports up to 710 MHz on individual outputs, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints in the MultiSynth™ architecture. For example, generating 473.33 MHz and 710 MHz concurrently is supported, but three or more >350 MHz outputs require integer-related frequencies or fallback to lower bands.

How does the SI5338C-B15672-GM handle loss-of-signal detection?

The SI5338C-B15672-GM provides hardware-based loss-of-signal (LOS) detection on all six input pins (IN1–IN6) with 2.6–5 µs response time and 0.01–1 µs release time. Detection status is reported via the open-drain INTR pin and readable through I²C registers. LOS triggers automatic switchover to backup reference if configured, and halts output clock generation to prevent metastability in downstream logic. This behavior is active in both PLL and buffer modes.

Is external programming required to use the SI5338C-B15672-GM in a PCIe system?

No. The SI5338C-B15672-GM is delivered pre-programmed for immediate use in PCIe Gen 3/4 systems with 156.25 MHz reference and four 100 MHz HCSL outputs. External I²C programming is optional and only needed for custom configurations - such as different output frequencies, formats, or spread-spectrum settings. ClockBuilder Pro software is provided free by Skyworks for advanced customization of the SI5338C-B15672-GM.

SI5338C-B15672-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: -

Type:: Clock Generator

PLL:: Yes with Bypass

Input:: CML, CMOS, HCSL, HSCT, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.98V, 2.25V ~ 2.75V, 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338C-B15672-GM FAQ

1.How can I place an order for SI5338C-B15672-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338C-B15672-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338C-B15672-GM reliable?

The price and inventory of SI5338C-B15672-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338C-B15672-GM is usually 5 days.

3.What payment methods are accepted for SI5338C-B15672-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338C-B15672-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338C-B15672-GM?

SI5338C-B15672-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338C-B15672-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338C-B15672-GM?

For technical support, including SI5338C-B15672-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338C-B15672-GM requirements.

6.How does Aetrix verify that SI5338C-B15672-GM is sourced from the original manufacturer or authorized distributors?

All SI5338C-B15672-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338C-B15672-GM meets industry standards.

7.What is the process for return or replacement of SI5338C-B15672-GM?

All SI5338C-B15672-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338C-B15672-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338C-B15672-GM part is unused and in its original packaging.

Return procedure for SI5338C-B15672-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…