Skyworks Solutions Inc. SI5338D-B04193-GM

Overview

SI5338D-B04193-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338D-B04193-GM datasheet, SI5338D-B04193-GM pinout, SI5338D-B04193-GM application, or SI5338D-B04193-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338D-B04193-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving one output channel. Each MultiSynth supports integer or fractional mode operation with ≤1 ppb frequency resolution and programmable initial phase offset (±45 ns).

It accepts six input references - including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - and supports flexible output configurations: LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML across four drivers, with independent VDDO per driver (1.4–3.63 V) and glitchless frequency increment/decrement (1 ppm steps).

Key Specifications

Pinout & Package

SI5338D-B04193-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family: IN1–IN6 (six reference inputs), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (four independent output supply rails), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and GND/RSVD_GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06189-GM, SI5338D-B04193-GM offers field-programmability and broader input reference support but higher jitter; compared with ICS853S01AGI-01LFT, it provides full any-frequency synthesis at the cost of increased design complexity and configuration overhead.

Availability

SI5338D-B04193-GM is available at Aetrix Electronics and suitable for PCIe timing, Ethernet switch/router clocking, broadcast video synchronization, and FPGA/processor clock distribution requiring stable component supply and long-term manufacturability.

Supply support for SI5338D-B04193-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, emphasizing flexibility, integration, and jitter performance in compact packages.

FAQ

What is the maximum output frequency supported by SI5338D-B04193-GM?

The SI5338D-B04193-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs and 350 MHz on SSTL/HSTL outputs. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to internal VCO constraints. All other outputs are limited to ≤350 MHz in that configuration.

Does SI5338D-B04193-GM support PCIe Gen 4 timing requirements?

Yes, SI5338D-B04193-GM meets PCIe Gen 4 common clock jitter specifications (≤0.45 ps RMS, 10 kHz–50 MHz) when configured with appropriate PLL bandwidth (2–4 or 2–5 MHz) and CDR = 10 MHz. Its 0.7 ps RMS typical phase jitter and documented PCIe Gen 4 compliance in the datasheet confirm suitability for Gen 4 root complex and endpoint timing.

How many independent supply rails does SI5338D-B04193-GM have for its outputs?

SI5338D-B04193-GM has four independent VDDO supply rails - VDDO0 through VDDO3 - each powering one differential output pair (CLK0A/B through CLK3A/B). Each rail accepts 1.4–3.63 V, enabling mixed-signal interfacing (e.g., 1.8 V LVDS to one FPGA bank and 3.3 V CMOS to another) without level shifters.

Can SI5338D-B04193-GM operate in clock buffer (PLL bypass) mode?

Yes, SI5338D-B04193-GM supports clock buffer mode with additive phase jitter as low as 0.165 ps RMS (12 kHz–20 MHz) using a 622.08 MHz differential input. In this mode, the PLL is bypassed and outputs directly replicate the input clock with minimal added jitter, useful for low-latency, low-noise fanout applications.

What software tools are available to configure SI5338D-B04193-GM?

Skyworks ClockBuilder Pro is the official GUI-based configuration tool for SI5338D-B04193-GM, enabling full register setup, jitter simulation, and .c/.h file generation for embedded initialization. The PCIe Clock Jitter Tool is also provided for validation against Intel's PCIe jitter compliance test suite.