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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338D-B05045-GMR

Name: SI5338D-B05045-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338D-B05045-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338D-B05045-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338D-B05045-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338D-B05045-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator featuring four independent differential clock outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338D-B05045-GMR datasheet, SI5338D-B05045-GMR pinout, SI5338D-B05045-GMR application, or SI5338D-B05045-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), programmable phase/frequency step resolution (<20 ps / 1 ppm), and 24-pin 4×4 mm QFN package with integrated loss-of-lock and loss-of-signal monitoring.

Technical Context

The SI5338D-B05045-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal (8–30 MHz) or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each output supports integer or fractional frequency synthesis with <1 ppb resolution and configurable loop bandwidth (1.6 MHz typical).

Its output stage provides per-driver voltage selection (1.5/1.8/2.5/3.3 V), independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and glitchless frequency/phase adjustment via dedicated pins or I²C. The device operates across –40 to +85 °C with core supply options of 1.8/2.5/3.3 V and output buffer supplies from 1.4 to 3.63 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock and SRNS requirements
Output Count & Type	4 differential outputs (CLK0A/B through CLK3A/B); supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with <1 ppb resolution
Input Flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, GMR suffix indicates green packaging
Operating Temp	–40 to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338D-B05045-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), pin 24 is bottom-right (GND). Power sequencing requires VDD before VDDOx. All ground pins (pins 17, 23, 24, and RSVD_GND) must be connected to solid ground plane.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML inputs up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential clock outputs	Four independent pairs; each pair supports format/voltage configuration and phase/frequency tuning
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs with independent fractional-N dividers
PCIe Gen 4 compliance	Meets Common Clock and SRNS jitter specs (≤0.45 ps RMS) without external filtering or reclocking
Per-output voltage control	Eliminates level-shifting components when driving mixed-voltage FPGAs, ASICs, or SerDes PHYs
Glitchless frequency tuning	1 ppm step size with ≤667 ns update time enables real-time dynamic clock rate adaptation
Programmable phase offset	±45 ns range in <20 ps steps allows precise skew alignment between high-speed parallel buses or multi-lane interfaces
Spread spectrum control	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) reduces EMI in dense PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched phase alignment. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and enabling per-port frequency margining.	Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE/25 GbE MAC/PHY interfaces in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet line rates from a single 25 MHz crystal reference. Use Value: Reduces BOM count and layout area versus fixed-frequency oscillators; supports IEEE 802.3bj/802.3by jitter requirements via programmable loop bandwidth.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder SoCs in broadcast infrastructure. IC Role / Device Role / Timing Role: High-frequency clock generator synthesizing 270 MHz, 540 MHz, and 720 MHz outputs from one crystal source. Use Value: Achieves sub-1 ps RMS jitter required for 4K/8K video transport; avoids jitter accumulation from cascaded PLLs.	Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal or Intel Agilex FPGA platforms. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage domains for core, memory, and I/O banks. Use Value: Enables optimal noise isolation via separate VDDO supplies; supports dynamic voltage/frequency scaling (DVFS) via I²C command.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched phase alignment.

Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and enabling per-port frequency margining.

Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE/25 GbE MAC/PHY interfaces in enterprise switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet line rates from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and layout area versus fixed-frequency oscillators; supports IEEE 802.3bj/802.3by jitter requirements via programmable loop bandwidth.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder SoCs in broadcast infrastructure.

IC Role / Device Role / Timing Role: High-frequency clock generator synthesizing 270 MHz, 540 MHz, and 720 MHz outputs from one crystal source.

Use Value: Achieves sub-1 ps RMS jitter required for 4K/8K video transport; avoids jitter accumulation from cascaded PLLs.

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal or Intel Agilex FPGA platforms.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage domains for core, memory, and I/O banks.

Use Value: Enables optimal noise isolation via separate VDDO supplies; supports dynamic voltage/frequency scaling (DVFS) via I²C command.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05045-GM	Higher integration: includes integrated crystal, smaller 3×3 mm package, lower power (32 mA typ), but limited to 3 outputs	Preferred for space-constrained designs where crystal integration simplifies layout and reduces component count	Select when board area and bill-of-materials reduction outweigh need for fourth output
ICS853S02IAGLF	Fixed-frequency, non-programmable; 2-output LVDS clock fanout buffer with 0.4 ps RMS jitter	Used only in static clock distribution scenarios requiring ultra-low additive jitter, not synthesis	Select only if design uses pre-defined frequencies and prioritizes lowest possible jitter over flexibility

Compared with Si5332A-D05045-GM and ICS853S02IAGLF, SI5338D-B05045-GMR uniquely delivers four independently programmable outputs with full any-frequency synthesis, making it optimal for complex multi-protocol systems requiring PCIe, Ethernet, and video timing from a single IC-without sacrificing jitter performance or thermal headroom.

Availability

SI5338D-B05045-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25 GbE routing, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338D-B05045-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, multi-protocol timing in data center, telecom, and broadcast equipment-enabling consolidation of discrete oscillators into a single, software-configurable clock source with deterministic jitter behavior.

FAQ

What is the maximum output frequency supported by SI5338D-B05045-GMR?

The SI5338D-B05045-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. Two outputs may simultaneously operate above 350 MHz (Fvco/4 and Fvco/6), but total unique high-frequency outputs are limited to two per device. This capability is confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6.

Does SI5338D-B05045-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338D-B05045-GMR is explicitly compliant with PCIe Gen 4 SRNS requirements, achieving ≤0.32 ps RMS jitter (typical) under specified test conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This is documented in Table 12 of the Skyworks Si5338 datasheet Rev. 1.6 and validated using the Skyworks PCIe Clock Jitter Tool.

Can SI5338D-B05045-GMR generate different output voltages simultaneously?

Yes, SI5338D-B05045-GMR supports independent output buffer supplies (VDDO0–VDDO3), allowing simultaneous generation of LVPECL (3.3 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (1.5 V) outputs. Each VDDO pin powers its respective output pair, enabling direct interfacing with mixed-voltage FPGAs and ASICs without external level shifters.

What is the minimum input clock frequency supported by SI5338D-B05045-GMR in PLL bypass mode?

In PLL bypass (clock buffer) mode, SI5338D-B05045-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2/IN5/IN6). However, loss-of-signal detection is only functional above 5 MHz. This behavior is specified in Table 6, Note 3 of the Skyworks datasheet Rev. 1.6.

How is SI5338D-B05045-GMR programmed and configured?

SI5338D-B05045-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output format, frequency, voltage, phase offset, spread spectrum, and alarm thresholds. Factory-programmed OTP NVM retains settings across power cycles, and runtime updates are supported without reset.

SI5338D-B05045-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338D-B05045-GMR FAQ

1.How can I place an order for SI5338D-B05045-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338D-B05045-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338D-B05045-GMR reliable?

The price and inventory of SI5338D-B05045-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338D-B05045-GMR is usually 5 days.

3.What payment methods are accepted for SI5338D-B05045-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338D-B05045-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338D-B05045-GMR?

SI5338D-B05045-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338D-B05045-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338D-B05045-GMR?

For technical support, including SI5338D-B05045-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338D-B05045-GMR requirements.

6.How does Aetrix verify that SI5338D-B05045-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338D-B05045-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338D-B05045-GMR meets industry standards.

7.What is the process for return or replacement of SI5338D-B05045-GMR?

All SI5338D-B05045-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338D-B05045-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338D-B05045-GMR part is unused and in its original packaging.

Return procedure for SI5338D-B05045-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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