Skyworks Solutions Inc. SI5338D-B05172-GMR
- Part No.:
- SI5338D-B05172-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338D-B05172-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,594
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Product details
Overview
SI5338D-B05172-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.
For engineers reviewing the SI5338D-B05172-GMR datasheet, SI5338D-B05172-GMR pinout, SI5338D-B05172-GMR application, or SI5338D-B05172-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus interface.
Technical Context
The SI5338D-B05172-GMR implements a two-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) feeding a fractional-N MultiSynth™ synthesizer per output channel. Each output supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage rail (VDDO0–VDDO3).
It features programmable initial phase offset (±45 ns), glitchless frequency increment/decrement in 1 ppm steps, and <20 ps phase step resolution. Loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and I²C register-based configuration via ClockBuilder Pro software complete its timing control framework.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL) |
| Frequency range per output | 0.16–710 MHz (LVPECL/LVDS); 0.16–250 MHz (HCSL); 0.16–200 MHz (CMOS); 0.16–350 MHz (SSTL/HSTL) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 common clock specs |
| Input reference support | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply & power | 1.8/2.5/3.3 V core (VDD); independent 1.5/1.8/2.5/3.3 V output buffers (VDDOx); 45 mA typical core current |
| Package & environment | 24-pin QFN, 4 × 4 mm; operating temperature –40 to +85 °C; JEDEC-compliant reflow profile |
Pinout & Package
SI5338D-B05172-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are standardized across Si5338 variants per Skyworks Rev. 1.6 datasheet (page 37).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD |
| CLK0A/CLK0B–CLK3A/CLK3B | Differential output pairs | Four independent output channels; each pair configurable for LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supply rails | Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing |
| SCL, SDA, INTR | I²C interface & status | Standard SMBus-compatible serial interface; open-drain interrupt for LOS/LOL events |
| VDD, GND, RSVD_GND | Core power & grounding | Single-core supply (1.71–3.63 V); dedicated ground pins and reserved ground pad for thermal/EMI control |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs with independent fractional-N dividers |
| PCIe compliance | Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter requirements (≤0.32 ps RMS) |
| Flexible output configuration | Each output supports format, voltage, slew rate, and termination control - enabling direct interface to FPGAs, ASICs, and SerDes PHYs |
| Spread spectrum | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI |
| Glitchless tuning | Independent frequency/phase increment/decrement via pin or I²C with ≤20 ps phase step resolution and sub-ppm frequency step size |
Applications
| PCIe Gen 4 Switch Fabric | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: High-speed switch fabric requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 endpoints and root complexes. IC Role / Device Role / Timing Role: Quad-output clock generator providing four low-jitter, independently configured 100 MHz HCSL clocks with Gen 4 common clock compliance. Use Value: Eliminates four discrete oscillators; meets PCIe Gen 4 TJ < 3.5 ps pk-pk and RMS jitter ≤0.45 ps at 100 MHz. |
Use Scenario: 10GbE line card needing precise 156.25 MHz and 312.5 MHz clocks for MAC/PHY synchronization and SerDes CDR lock. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact frequencies from a single 25 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter at 156.25 MHz, satisfying IEEE 802.3bj Annex 83F and OIF CEI-28G requirements. |
| FPGA-Based Broadcast Video Router | Telecom MSAN with Multi-Standard Sync |
Use Scenario: Broadcast video infrastructure requiring SMPTE ST 2082 (27 Gbps) pixel clock (270 MHz) and ancillary timing (74.25 MHz, 148.5 MHz). IC Role / Device Role / Timing Role: Multi-format clock source delivering LVDS and HCSL outputs simultaneously at different voltages and frequencies. Use Value: Supports concurrent 270 MHz LVDS and 74.25 MHz HCSL outputs with <100 ps output-to-output skew and ±45 ns programmable phase alignment. |
Use Scenario: Multi-service access node supporting synchronous Ethernet (SyncE), PTP, and TDM interfaces with distinct frequency requirements (e.g., 8 kHz, 2.048 MHz, 153.6 MHz). IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner accepting E1/T1 or SyncE references and generating telecom-grade outputs. Use Value: Delivers OC-12–compliant jitter (≤1 ps RMS) and supports external feedback for zero-delay mode in master clock applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B-GM | Same Si5338 family; factory-programmed OTP variant with fixed configuration; no field reprogramming via I²C | Limited to pre-defined frequency plans; unsuitable for dynamic frequency adjustment or multi-design reuse | Select when production volume justifies OTP NRE cost and configuration stability is guaranteed |
| LMK04832ISQE/NOPB | Two PLLs (jitter cleaner + synthesizer); higher integration (integrated LDOs, dual-loop architecture); 3.15 ps RMS integrated jitter floor | Better suited for ultra-low-jitter cleaning of noisy references; larger 64-pin WQFN package | Prefer when input reference quality is poor or sub-0.5 ps RMS jitter is required post-cleaning |
Compared with SI5338D-B05172-GMR, Si5338A-B-GM trades field programmability for lower unit cost and faster startup, while LMK04832 offers superior jitter cleaning but requires more board area and power - making SI5338D-B05172-GMR optimal for space-constrained, multi-frequency, reconfigurable designs.
Availability
SI5338D-B05172-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 endpoint, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and full I²C configurability.
Supply support for SI5338D-B05172-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems - designed specifically for PCIe, Ethernet, broadcast video, and telecom applications demanding precision frequency synthesis and flexible output formatting.
FAQ
What is the primary function of the SI5338D-B05172-GMR?
The SI5338D-B05172-GMR is an I²C-programmable quad clock generator that synthesizes up to four independent, low-jitter output frequencies from a single input reference. It replaces multiple discrete oscillators in systems like PCIe switches and FPGA platforms, supporting formats including LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL with 0.7 ps RMS typical phase jitter.
Does the SI5338D-B05172-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338D-B05172-GMR meets PCIe Gen 4 common clock specifications with ≤0.45 ps RMS jitter (12 kHz–20 MHz) at 100 MHz output, verified per PCI-SIG Base Specification 4.0 rev. 0.5. Its MultiSynth™ architecture and optimized PLL loop bandwidth (2–5 MHz) ensure compliance without external filtering or reclocking.
How is the SI5338D-B05172-GMR configured during system operation?
The SI5338D-B05172-GMR is configured via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. Configuration includes output frequency, format, voltage, spread spectrum, phase offset, and alarm thresholds. Field updates are supported without hardware changes, and pin-controlled frequency/phase adjustments enable real-time tuning.
What package and thermal characteristics does the SI5338D-B05172-GMR have?
The SI5338D-B05172-GMR uses a 24-pin QFN package measuring 4 × 4 mm with an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C ambient. The package supports standard reflow profiles up to 260 °C peak.
Can the SI5338D-B05172-GMR generate frequencies above 350 MHz?
Yes - the SI5338D-B05172-GMR supports up to 710 MHz on LVPECL/LVDS outputs and 350 MHz on SSTL/HSTL. However, only two unique frequencies above 350 MHz may be generated simultaneously (Fvco/4 and Fvco/6), as constrained by the internal VCO architecture and synthesis stage limitations documented in the Si5338 datasheet section 3.3.
SI5338D-B05172-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338D-B05172-GMR FAQ
1.How can I place an order for SI5338D-B05172-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338D-B05172-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338D-B05172-GMR reliable?
The price and inventory of SI5338D-B05172-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338D-B05172-GMR is usually 5 days.
3.What payment methods are accepted for SI5338D-B05172-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338D-B05172-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338D-B05172-GMR?
SI5338D-B05172-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338D-B05172-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338D-B05172-GMR?
For technical support, including SI5338D-B05172-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338D-B05172-GMR requirements.
6.How does Aetrix verify that SI5338D-B05172-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338D-B05172-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338D-B05172-GMR meets industry standards.
7.What is the process for return or replacement of SI5338D-B05172-GMR?
All SI5338D-B05172-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338D-B05172-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338D-B05172-GMR part is unused and in its original packaging.
Return procedure for SI5338D-B05172-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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