Skyworks Solutions Inc. SI5338D-B09539-GMR
- Part No.:
- SI5338D-B09539-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- -
- Datasheet:
-
SI5338D-B09539-GMR.pdf
- Description:
- IC CLOCK GENERATOR QUAD 24QFN
- Quantity:
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Product details
Overview
SI5338D-B09539-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs - used in FPGA clocking, Ethernet switch timing, and PCIe-based server platforms.
For engineers reviewing the SI5338D-B09539-GMR datasheet, SI5338D-B09539-GMR pinout, SI5338D-B09539-GMR application, or SI5338D-B09539-GMR equivalent, key selection criteria include differential output jitter performance, I²C programmability across four independent synthesis paths, PCIe Gen 4 common-clock jitter compliance (0.15–0.45 ps RMS), and 24-QFN package compatibility with 4×4 mm PCB footprint constraints.
Technical Context
The SI5338D-B09539-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers per output. Each output supports integer or fractional mode operation, enabling true zero-ppm frequency accuracy and <20 ps programmable phase step resolution.
It accepts multiple input references - 8–30 MHz crystal, 5–200 MHz CMOS, or up to 710 MHz differential - and routes them through configurable dividers (R0–R3) before the VCO stage. Output drivers support independent voltage supply (1.5/1.8/2.5/3.3 V) and format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), with spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate) on any channel.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | Four independent differential or single-ended clock outputs (CLK0A/B to CLK3A/B) |
| Frequency range | 0.16–710 MHz per output; supports simultaneous >350 MHz outputs only at Fvco/4 and Fvco/6 |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock spec (0.15–0.45 ps RMS) |
| Input reference | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply voltages | Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp. | –40 °C to +85 °C ambient; junction-to-ambient thermal resistance θJA = 37 °C/W |
Pinout & Package
SI5338D-B09539-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept AC-coupled 5–710 MHz differential reference; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support DC-coupled 5–200 MHz CMOS/SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs | Four independent output channels; each pair (e.g., CLK0A/CLK0B) provides complementary signals |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output bank; enable mixed-voltage signaling |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) or loss-of-signal (LOS); active-low |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable zero-ppm accuracy and glitchless frequency tuning in 1 ppm steps |
| PCIe Gen 4 compliance | Meets PCIe Base Spec 4.0 common-clock jitter requirements (0.15–0.45 ps RMS) without external filtering |
| Programmable phase offset | ±45 ns initial phase adjustment per output with <20 ps step resolution for skew management |
| Spread-spectrum control | Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, down-spread default |
| Flexible input support | Five input options: crystal oscillator, CMOS, SSTL, HSTL, or differential - selectable per design via register configuration |
Applications
| Processor and FPGA Clocking | PCIe Gen 1–4 Timing |
|---|---|
Use Scenario: Providing synchronized, low-jitter clocks to multi-core processors and high-speed FPGAs in telecom line cards and AI accelerators. IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent, programmable frequencies to CPU cores, memory interfaces, and SerDes blocks. Use Value: Eliminates need for multiple discrete oscillators; enables dynamic frequency scaling and phase alignment across heterogeneous logic domains. | Use Scenario: Generating compliant reference clocks for PCIe root complexes and endpoints in servers and storage systems. IC Role / Device Role / Timing Role: Common-clock source meeting PCIe Gen 4 SRNS jitter specs (0.11–0.32 ps RMS) with integrated spread spectrum. Use Value: Reduces EMI without external SSC circuitry; supports both common-clock and separate-reference-no-spread (SRNS) modes. |
| Ethernet Switch/Routing | Broadcast Video Timing |
Use Scenario: Supplying precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 1/10 GbE PHYs and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Low-jitter (<0.7 ps RMS) clock synthesizer supporting IEEE 802.3 standards and PTP synchronization. Use Value: Enables deterministic latency and jitter-controlled packet forwarding; supports multiple line rates from single device. | Use Scenario: Generating SMPTE-compliant video clocks (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) for broadcast encoders, decoders, and frame synchronizers. IC Role / Device Role / Timing Role: Any-frequency clock generator with sub-20 ps phase step resolution for genlock and frame-accurate timing alignment. Use Value: Replaces multiple fixed-frequency oscillators; supports seamless switching between SD/HD/UHD formats via I²C reprogramming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08586-GM | 8-output, higher integration; supports JESD204B deterministic latency; lower jitter (0.35 ps RMS typ) | Targeted at high-channel-count data converters and radar systems requiring deterministic delay | Select when >4 outputs or sub-0.5 ps jitter is required; not pin-compatible |
| ICS8430I-01T | Quad LVDS output only; fixed 100/125/156.25 MHz outputs; no I²C programming; 1.2 ps RMS jitter | Cost-sensitive, static-clock applications like legacy networking gear | Select only for non-programmable, fixed-frequency use cases; lacks any-frequency synthesis |
Compared with Si5332A-D08586-GM and ICS8430I-01T, the SI5338D-B09539-GMR uniquely balances programmability, jitter performance, and pin count - offering full I²C configurability across four outputs in a compact 24-QFN, while avoiding overdesign for mid-channel-count applications.
Availability
SI5338D-B09539-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, Ethernet switching infrastructure, and FPGA-based broadcast video equipment requiring stable component supply and long-term lifecycle support.
Supply support for SI5338D-B09539-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers highly configurable, low-jitter clock generators targeting high-speed digital systems where precision timing, programmability, and space-constrained layouts are critical - especially in PCIe, Ethernet, and FPGA-based platforms.
FAQ
What is the maximum output frequency supported by SI5338D-B09539-GMR in LVPECL mode?
The SI5338D-B09539-GMR supports up to 710 MHz in LVPECL output mode, as confirmed in Table 6 of the datasheet. This applies when using differential outputs with appropriate termination and layout practices. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), and jitter performance remains within specification (0.7 ps RMS typical) under recommended operating conditions.
Does SI5338D-B09539-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338D-B09539-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), verified per PCI Express Base Specification 4.0 rev. 0.5. This requires configuring the PLL loop bandwidth to 2–4 or 2–5 MHz and setting the CDR frequency to 10 MHz - all achievable via I²C register writes in the SI5338D-B09539-GMR's internal NVM or RAM.
Can SI5338D-B09539-GMR generate four different output frequencies simultaneously?
Yes, SI5338D-B09539-GMR can synthesize four independent output frequencies simultaneously - each configured via its own MultiSynth™ engine. Supported ranges include 0.16–710 MHz (LVPECL/LVDS), 0.16–250 MHz (HCSL), and 0.16–200 MHz (CMOS), with zero-ppm accuracy and independent format/voltage selection per output bank.
What is the core supply current consumption of SI5338D-B09539-GMR at full operation?
At full operation - 100 MHz on all four outputs with a 25 MHz reference clock - the SI5338D-B09539-GMR draws 45 mA typical core supply current (IDD), with a maximum of 60 mA across the –40 °C to +85 °C temperature range and nominal 1.8/2.5/3.3 V supply, as specified in Table 3 of the datasheet.
Is ClockBuilder Pro software required to configure SI5338D-B09539-GMR?
No, ClockBuilder Pro is optional but strongly recommended for SI5338D-B09539-GMR configuration. The device supports direct I²C register access for full customization; however, ClockBuilder Pro automates complex MultiSynth™ calculations, validates jitter compliance, generates configuration files, and exports to hardware via USB adapter - significantly reducing development time versus manual register programming.
SI5338D-B09539-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5338D-B09539-GMR FAQ
1.How can I place an order for SI5338D-B09539-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338D-B09539-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338D-B09539-GMR reliable?
The price and inventory of SI5338D-B09539-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338D-B09539-GMR is usually 5 days.
3.What payment methods are accepted for SI5338D-B09539-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338D-B09539-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338D-B09539-GMR?
SI5338D-B09539-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338D-B09539-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338D-B09539-GMR?
For technical support, including SI5338D-B09539-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338D-B09539-GMR requirements.
6.How does Aetrix verify that SI5338D-B09539-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338D-B09539-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338D-B09539-GMR meets industry standards.
7.What is the process for return or replacement of SI5338D-B09539-GMR?
All SI5338D-B09539-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338D-B09539-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338D-B09539-GMR part is unused and in its original packaging.
Return procedure for SI5338D-B09539-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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