Skyworks Solutions Inc. SI5338D-B09540-GMR

Overview

SI5338D-B09540-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 timing systems.

For engineers reviewing the SI5338D-B09540-GMR datasheet, SI5338D-B09540-GMR pinout, SI5338D-B09540-GMR application, or SI5338D-B09540-GMR equivalent, key selection criteria include differential output jitter compliance (PCIe Gen 4 SRNS), independent per-output voltage configuration (1.5–3.3 V), spread-spectrum control (0.5–5.0% down-spread), and I²C-based field reprogramming capability.

Technical Context

The SI5338D-B09540-GMR implements a two-stage PLL architecture: a high-stability reference PLL (stage 1) locks to an external crystal (8–30 MHz) or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (stage 2) generating each output. Each synthesizer supports integer/fractional mode operation with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement.

Its output stage provides per-driver voltage selection (1.5/1.8/2.5/3.3 V), configurable drive strength, and flexible signal format mapping - including simultaneous differential (LVPECL/LVDS/HCSL/CML) and single-ended (CMOS/SSTL/HSTL) outputs - all under full I²C/SMBus control with loss-of-lock and loss-of-signal monitoring.

Key Specifications

Pinout & Package

SI5338D-B09540-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 variants per Skyworks documentation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-B09540-GM, SI5338D-B09540-GMR offers field-updatable configuration via I²C, while LMK04832ISQE/NOPB trades synthesis flexibility for superior jitter cleaning - making SI5338D-B09540-GMR optimal for compact, reconfigurable multi-clock systems.

Availability

SI5338D-B09540-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, broadcast video master clocking, and FPGA-based telecom line card applications requiring stable component supply and long-term lifecycle support.

Supply support for SI5338D-B09540-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generators for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, emphasizing field programmability and multi-format output flexibility.

FAQ

What is the maximum output frequency supported by SI5338D-B09540-GMR?

The SI5338D-B09540-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the internal VCO architecture. All outputs maintain 0.7 ps RMS jitter at these rates when using differential signaling and low-noise reference inputs.

Does SI5338D-B09540-GMR support PCIe Gen 4 timing requirements?

Yes, SI5338D-B09540-GMR meets PCIe Gen 4 Common Clock specifications with ≤0.45 ps RMS jitter (12 kHz–20 MHz) and complies with Gen 3 Separate Reference No Spread (SRNS) requirements at ≤0.32 ps RMS. These values are measured per Skyworks AN562 methodology using 100 MHz HCSL outputs and validated with the Skyworks PCIe Clock Jitter Tool.

How many independent supply voltages can be applied to SI5338D-B09540-GMR outputs?

SI5338D-B09540-GMR supports four independent output buffer supply voltages (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components - such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V legacy logic - without external level translators, reducing BOM cost and signal integrity risk.

Can SI5338D-B09540-GMR operate in clock buffer (PLL bypass) mode?

Yes, SI5338D-B09540-GMR supports clock buffer mode where the PLL is bypassed and input clocks pass directly to outputs with minimal additive jitter (0.165 ps RMS, 12 kHz–20 MHz). This mode requires specific register configuration and supports input frequencies from 1 MHz (with limited LOS functionality) to 200 MHz for single-ended and up to 710 MHz for differential inputs.

What development tools are available for configuring SI5338D-B09540-GMR?

Skyworks ClockBuilder Pro software is the official configuration tool for SI5338D-B09540-GMR, enabling GUI-based frequency planning, jitter analysis, register map generation, and I²C programming file export. The tool integrates PCIe jitter validation and supports hardware evaluation via USB-to-I²C adapters. Configuration files can be stored in the device's on-chip OTP or loaded dynamically over I²C during system boot.