Skyworks Solutions Inc. SI5338E-B-GMR
- Part No.:
- SI5338E-B-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338E-B-GMR.pdf
- Description:
- IC CLK GENERATOR I2C PROGR 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338E-B-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typical) across LVPECL/LVDS/HCSL/CMOS/SSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA-based systems.
For engineers reviewing the SI5338E-B-GMR datasheet, SI5338E-B-GMR pinout, SI5338E-B-GMR application, or SI5338E-B-GMR equivalent, this page provides verified pin functions, PCIe Gen 4 SRNS-compliant jitter performance, output voltage configurability per driver (1.5–3.3 V), spread-spectrum control, and phase/frequency adjustment resolution down to 20 ps / 1 ppm - all critical for high-speed serial interface clocking.
Technical Context
The SI5338E-B-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four outputs operates independently with dedicated M/N/R dividers and configurable output drivers.
It supports both free-running synthesis and zero-delay buffer mode (PLL bypass), with loss-of-lock and loss-of-signal monitoring, programmable initial phase offset (±45 ns), and independent frequency increment/decrement via pin or I²C - enabling dynamic clock tuning without glitches in real-time systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock and SRNS requirements. |
| Output Count & Type | Four differential outputs (CLK0A/B through CLK3A/B); supports up to eight single-ended or mixed configurations. |
| Frequency Range | 0.16–710 MHz per output; includes PCIe Gen 4 (100 MHz HCSL), 10GbE (156.25 MHz), and broadcast video (27 MHz) coverage. |
| Input Flexibility | Accepts 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference. |
| Supply Voltages | Core: 1.8/2.5/3.3 V; independent output buffers: 1.5/1.8/2.5/3.3 V per driver - enables mixed-voltage system interfacing. |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with high-density PCB layouts and automated assembly. |
| Operating Temp | –40 °C to +85 °C ambient - qualified for industrial and telecom infrastructure environments. |
Pinout & Package
SI5338E-B-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.6 datasheet (page 33).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled. |
| IN3, IN4 | Single-ended reference inputs | Support 5–200 MHz CMOS-level clocks; configurable as primary or backup reference. |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML/SSTL with per-driver VDDO. |
| VDDO0–VDDO3 | Output buffer supply rails | Independent 1.5–3.3 V supplies per output bank - enables mixed-signal voltage domain interfacing. |
| SCL, SDA | I²C configuration interface | Standard SMBus-compatible 100/400 kHz interface; supports in-system programming and runtime reconfiguration. |
| INTR | Interrupt output | Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error events. |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for noisy system environments. |
| GND, RSVD_GND | Ground connections | Multiple GND pins including reserved ground for noise isolation; requires solid thermal pad connection. |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs simultaneously. |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) in common clock mode satisfies PCIe Base Spec 4.0 rev. 0.5. |
| Per-output voltage control | Each output driver powered by dedicated VDDO rail (1.5/1.8/2.5/3.3 V) - eliminates level-shifter components. |
| Glitchless frequency tuning | Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps with <667 ns update time above 18 MHz. |
| Programmable spread spectrum | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range. |
| Phase adjustment resolution | ±45 ns range with <20 ps step size per output - enables fine-grained skew compensation in multi-lane interfaces. |
Applications
| PCIe Gen 4 Add-in Card | Ethernet Switch Timing |
|---|---|
Use Scenario: High-bandwidth GPU or NVMe add-in card requiring synchronized 100 MHz HCSL clocks for root complex and endpoint links. IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Gen 4 common clock and SRNS-compliant reference with <0.32 ps RMS jitter. Use Value: Eliminates need for multiple discrete oscillators; supports dynamic frequency scaling and thermal-aware clock margining. |
Use Scenario: 10GbE/25GbE switch ASIC requiring low-jitter 156.25 MHz and 312.5 MHz clocks with tight inter-output skew. IC Role / Device Role / Timing Role: Programmable clock source generating four independent frequencies with <100 ps output-to-output skew. Use Value: Enables single-chip timing for multi-port PHYs while maintaining IEEE 802.3bj jitter compliance. |
| Broadcast Video Sync Generator | FPGA-Based Test Equipment |
Use Scenario: SMPTE ST 2082 (12G-SDI) equipment needing precise 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with sub-nanosecond phase alignment. IC Role / Device Role / Timing Role: Multi-frequency synthesizer with programmable initial phase offset (±45 ns) and <20 ps phase step resolution. Use Value: Replaces crystal+divider chains; allows real-time phase correction to compensate for cable delay mismatches. |
Use Scenario: Automated test equipment using FPGA fabric for protocol analysis, requiring configurable clocks for MIPI D-PHY, PCIe, and DDR interfaces. IC Role / Device Role / Timing Role: Flexible clock source supporting LVDS (for DDR), HCSL (for PCIe), and CMOS (for control logic) from one device. Use Value: Reduces BOM count and layout area; simplifies firmware-driven clock reconfiguration during test mode switching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D-GM | Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), but larger 32-QFN package. | Better suited for multi-ASIC systems requiring >4 clocks or tighter jitter budgets (e.g., 5G baseband). | Select Si5332A-D-GM when >4 outputs or sub-0.5 ps jitter is required; SI5338E-B-GMR remains optimal for cost-sensitive 4-output PCIe/Ethernet designs. |
| ICS8430I-01LG | Fixed-frequency, non-programmable quad LVDS generator; no I²C interface or MultiSynth™ flexibility. | Limited to static clock trees; cannot support dynamic frequency translation or spread-spectrum requirements. | Choose ICS8430I-01LG only for legacy designs with fixed 100/125/156.25 MHz outputs and no reprogramming needs. |
Compared with Si5332A-D-GM and ICS8430I-01LG, the SI5338E-B-GMR uniquely balances programmability, PCIe Gen 4 compliance, and compact 4×4 mm footprint - making it the preferred choice for space-constrained, multi-standard timing in next-gen networking and compute platforms.
Availability
SI5338E-B-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 add-in cards, 10GbE switch timing, broadcast video sync generators, and FPGA-based test equipment requiring stable component supply and long-term design-in support.
Supply support for SI5338E-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The SI5338E-B-GMR belongs to Skyworks' Si5338 family of any-frequency clock generators, designed specifically for replacing multiple crystal oscillators in high-speed serial interface applications including PCIe, Ethernet, and broadcast video.
FAQ
What is the maximum output frequency supported by the SI5338E-B-GMR?
The SI5338E-B-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS - with two outputs capable of simultaneous >350 MHz operation (Fvco/4 and Fvco/6). This enables direct generation of PCIe Gen 4 (100 MHz), 10GbE (156.25 MHz), and 12G-SDI (74.25/148.5 MHz) clocks without external dividers. The SI5338E-B-GMR's MultiSynth™ engine ensures integer or fractional synthesis across the full range.
Does the SI5338E-B-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, the SI5338E-B-GMR is explicitly compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This is validated per PCI-Express Base Specification 4.0 rev. 0.5 and confirmed in Skyworks' AN562 application note. The SI5338E-B-GMR's low additive jitter and robust power supply rejection ensure reliable operation in high-noise server and accelerator card environments.
Can the SI5338E-B-GMR generate different output voltages simultaneously?
Yes, the SI5338E-B-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enabling simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without external level shifters. This capability is confirmed in Table 6 of the datasheet and directly supports mixed-voltage SoC/FPGA interfaces. The SI5338E-B-GMR's per-driver voltage control reduces BOM count and improves signal integrity in heterogeneous systems.
How is the SI5338E-B-GMR programmed, and what tools are required?
The SI5338E-B-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software - a free GUI tool that generates configuration files, validates settings against jitter and electrical constraints, and supports in-system programming. The SI5338E-B-GMR also supports pin-controlled frequency/phase adjustments (PINC/FDEC/OEB) for runtime tuning without host processor intervention. All register maps and initialization sequences are documented in the SI5338 datasheet Rev. 1.6.
What package and thermal characteristics does the SI5338E-B-GMR have?
The SI5338E-B-GMR uses a 24-pin QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load within the –40 °C to +85 °C industrial temperature range. The SI5338E-B-GMR's low 45 mA typical core current and optimized thermal pad layout simplify thermal design in dense PCBs - especially critical for PCIe add-in cards and telecom line cards where airflow is limited.
SI5338E-B-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- Ethernet, Fibre Channel, PCI Express (PCIe), Telecom
- Input:
- CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal
- Output:
- HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 350MHz
- Voltage - Supply:
- 1.71V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338E-B-GMR FAQ
1.How can I place an order for SI5338E-B-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338E-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338E-B-GMR reliable?
The price and inventory of SI5338E-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338E-B-GMR is usually 5 days.
3.What payment methods are accepted for SI5338E-B-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338E-B-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338E-B-GMR?
SI5338E-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338E-B-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338E-B-GMR?
For technical support, including SI5338E-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338E-B-GMR requirements.
6.How does Aetrix verify that SI5338E-B-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338E-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338E-B-GMR meets industry standards.
7.What is the process for return or replacement of SI5338E-B-GMR?
All SI5338E-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338E-B-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338E-B-GMR part is unused and in its original packaging.
Return procedure for SI5338E-B-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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