Skyworks Solutions Inc. SI5338F-B04077-GMR
- Part No.:
- SI5338F-B04077-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338F-B04077-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338F-B04077-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed networking and FPGA timing applications.
For engineers reviewing the SI5338F-B04077-GMR datasheet, SI5338F-B04077-GMR pinout, SI5338F-B04077-GMR application, or SI5338F-B04077-GMR equivalent, this page delivers verified specifications, validated pin functions, real-world use cases in PCIe and Ethernet systems, and two confirmed alternative parts with documented technical differences.
Technical Context
The SI5338F-B04077-GMR implements a dual-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks per output channel. Each output supports integer or fractional frequency synthesis with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement in 1 ppm steps.
It features configurable output supply voltages (1.5/1.8/2.5/3.3 V per driver), spread-spectrum control (0.5–5.0% deviation, 33–63 kHz modulation), loss-of-lock and loss-of-signal alarms, and I²C/SMBus interface with ClockBuilder Pro software support. The device operates across –40 to +85 °C with 1.8/2.5/3.3 V core supply and 45 mA typical core current at 100 MHz on all outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements |
| Output Count & Type | 4 differential outputs (CLK0A/B through CLK3A/B) - supports simultaneous LVPECL, LVDS, HCSL, or CML signaling |
| Frequency Range | 0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 212.5 MHz |
| Input Flexibility | 6 inputs: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm - enables dense PCB layout in switch/router line cards and server motherboards |
| Operating Temp | –40 to +85 °C - qualified for industrial and telecom infrastructure environments |
Pinout & Package
SI5338F-B04077-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet (pages 33–37).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias |
| CLK0A/CLK0B through CLK3A/CLK3B | Differential output pairs | Four independent output channels; each configurable for LVPECL/LVDS/HCSL/CML format and voltage |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V per output bank - enables mixed-voltage system interfacing |
| SCL/SDA | I²C interface | Standard SMBus-compatible serial bus (up to 400 kHz) for configuration and status readback |
| INTR | Interrupt output | Open-drain alarm signal for loss-of-lock, loss-of-signal, or configuration error events |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply with >60 dB PSRR - simplifies power delivery design |
| GND / RSVD_GND | Ground connections | Multiple dedicated ground pins and thermal pad - critical for low-jitter performance and EMI control |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external VCXOs |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter in common clock mode meets PCIe Base Spec 4.0 rev 0.5 requirements |
| Glitchless frequency tuning | Independent ±1 ppm step frequency increment/decrement via pin or I²C - enables dynamic rate adaptation in OTN or CPRI links |
| Programmable phase offset | ±45 ns per output with <20 ps step resolution - supports skew compensation across multi-lane SerDes interfaces |
| Spread spectrum control | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions in compact enclosures |
Applications
| PCIe Gen 3/4 Switch Timing | Ethernet 10GbE Line Card |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switches and endpoint devices in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter clocks with precise phase alignment and spread-spectrum capability. Use Value: Eliminates four discrete oscillators while meeting PCIe SRNS jitter spec (≤0.32 ps RMS) and reducing board area by >60%. | Use Scenario: Generating 156.25 MHz and 125 MHz clocks for 10GbE PHYs and MACs on telecom line cards with strict EMI limits. IC Role / Device Role / Timing Role: Configurable clock source supporting both LVDS and HCSL outputs at different voltages on same device. Use Value: Enables single-device timing for multi-rate Ethernet interfaces while using spread spectrum to pass CISPR-32 Class A radiated emissions tests. |
| FPGA-Based Broadcast Video System | MSAN/DSLAM Synchronization |
Use Scenario: Delivering frame-synchronized 27 MHz, 74.25 MHz, and 148.5 MHz clocks to video processing FPGAs and serializers in broadcast equipment. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE ST 292/372/425 rates with sub-ns phase adjustability. Use Value: Replaces crystal+PLL combos with single-chip solution achieving <10 ps cycle-cycle jitter - critical for artifact-free HD/4K video transport. | Use Scenario: Providing stratum-3–equivalent timing to DSLAM line cards requiring IEEE 1588 PTP grandmaster clock synchronization. IC Role / Device Role / Timing Role: Low-jitter clock generator accepting GPS-disciplined 10 MHz reference and synthesizing 1.544/2.048/155.52 MHz outputs. Use Value: Meets ITU-T G.823/G.824 wander and jitter masks with 0.7 ps RMS phase noise - ensures stable TDM and ATM cell timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B04083-GM | Same Si5338 family; factory-programmed with different default frequency configuration (B04083 vs B04077); identical pinout, specs, and package | Pre-configured for alternate output set (e.g., 125/156.25/312.5 MHz); requires no I²C programming for that specific use case | Select when pre-programmed frequencies match target design - reduces bring-up time versus field-programmable SI5338F-B04077-GMR |
| ICS853S01AGI-01LFT | Fixed-function 4-output LVDS generator (no I²C, no frequency flexibility); 1.2 ps RMS jitter; 3.3 V only; 32-pin TQFP | Limited to fixed 100/125/156.25/200 MHz outputs; no spread spectrum or phase adjustment | Choose for cost-sensitive, static-clock applications where programmability is unnecessary and board space allows larger TQFP package |
Compared with Si5338A-B04083-GM (pre-programmed variant) and ICS853S01AGI-01LFT (fixed-frequency alternative), SI5338F-B04077-GMR provides full field programmability, lowest jitter, and smallest footprint - making it optimal for high-performance, multi-standard systems requiring design flexibility and EMI control.
Availability
SI5338F-B04077-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line card clocking, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338F-B04077-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and CPRI - designed to replace multiple crystals and simplify timing architecture in datacenter and telecom infrastructure.
FAQ
What is the primary function of the SI5338F-B04077-GMR in a PCIe Gen 4 system?
The SI5338F-B04077-GMR serves as a quad-output, low-jitter clock generator providing compliant 100 MHz reference clocks to PCIe Gen 4 switches and endpoints. Its 0.15–0.45 ps RMS jitter in common clock mode meets PCI-SIG Base Specification 4.0 requirements, and its independent output configuration supports mixed-voltage SerDes interfaces without external level shifters. SI5338F-B04077-GMR replaces up to four discrete oscillators while maintaining sub-1 ps phase noise integrity.
Does the SI5338F-B04077-GMR support spread-spectrum clocking, and how is it configured?
Yes, the SI5338F-B04077-GMR supports fully configurable spread-spectrum clocking on any output: deviation range 0.5–5.0%, modulation rate 33–63 kHz, and selectable up/down-spread direction. Configuration is performed via I²C register writes using ClockBuilder Pro software or direct register access. SI5338F-B04077-GMR applies SSC independently per output, enabling EMI reduction in noise-sensitive subsystems like 10GbE PHYs without affecting other clock domains.
Can the SI5338F-B04077-GMR generate different output voltages simultaneously on its four channels?
Yes, the SI5338F-B04077-GMR supports independent output supply voltages: VDDO0 through VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on separate channels - essential for interfacing with heterogeneous logic families in FPGA-based systems. SI5338F-B04077-GMR maintains full specification compliance across all supported VDDO combinations.
What input reference sources does the SI5338F-B04077-GMR accept?
The SI5338F-B04077-GMR accepts six input reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). Inputs are selected via register configuration; IN1/IN2 and IN5/IN6 are differential pairs, while IN3/IN4 are single-ended. SI5338F-B04077-GMR automatically detects and conditions input signals, supporting both buffered and crystal oscillator modes without external components.
How is phase alignment controlled across the four outputs of the SI5338F-B04077-GMR?
The SI5338F-B04077-GMR provides independent programmable phase offset on each output with ±45 ns range and <20 ps step resolution. Phase is adjusted digitally via I²C or pin control (PINC/FDEC), enabling precise skew compensation between SerDes lanes or multi-chip synchronization. SI5338F-B04077-GMR achieves sub-100 ps output-to-output skew under matched load conditions - critical for JESD204B/C and CPRI applications.
SI5338F-B04077-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338F-B04077-GMR FAQ
1.How can I place an order for SI5338F-B04077-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338F-B04077-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338F-B04077-GMR reliable?
The price and inventory of SI5338F-B04077-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338F-B04077-GMR is usually 5 days.
3.What payment methods are accepted for SI5338F-B04077-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338F-B04077-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338F-B04077-GMR?
SI5338F-B04077-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338F-B04077-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338F-B04077-GMR?
For technical support, including SI5338F-B04077-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338F-B04077-GMR requirements.
6.How does Aetrix verify that SI5338F-B04077-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338F-B04077-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338F-B04077-GMR meets industry standards.
7.What is the process for return or replacement of SI5338F-B04077-GMR?
All SI5338F-B04077-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338F-B04077-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338F-B04077-GMR part is unused and in its original packaging.
Return procedure for SI5338F-B04077-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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