Skyworks Solutions Inc. SI5338F-B04078-GM

Overview

SI5338F-B04078-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338F-B04078-GM datasheet, SI5338F-B04078-GM pinout, SI5338F-B04078-GM application, or SI5338F-B04078-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe Gen 4 jitter compliance, exact package mapping (24-QFN, 4 × 4 mm), and two field-validated alternative parts for frequency-flexible clock synthesis designs.

Technical Context

The SI5338F-B04078-GM implements a dual-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports 5–710 MHz differential, 5–350 MHz SSTL/HSTL, or 5–200 MHz CMOS references - including external crystals from 8–30 MHz.

All four outputs support LVPECL/LVDS (0.16–710 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), and SSTL/HSTL (0.16–350 MHz), with independent VDDO selection (1.5/1.8/2.5/3.3 V) and per-output phase/frequency adjustment at <20 ps and 1 ppm resolution.

Key Specifications

Pinout & Package

SI5338F-B04078-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with SI5338F-B04078-GM, the Si5332A offers higher channel count and lower jitter but demands layout changes, while the ICS8430I sacrifices configurability for simplicity and lower unit cost-neither is pin-compatible, and both require functional validation for PCIe Gen 4 or mixed-voltage use cases.

Availability

SI5338F-B04078-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, Ethernet switching infrastructure, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338F-B04078-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.

The Si5338 product line delivers highly flexible, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and Fibre Channel-enabling system architects to consolidate timing resources and simplify clock tree design.

FAQ

What is the maximum output frequency supported by SI5338F-B04078-GM in LVPECL mode?

The SI5338F-B04078-GM supports up to 710 MHz in LVPECL mode when operating with differential outputs. This capability is validated per Table 6 of the datasheet and applies to any of its four output pairs (CLK0A/B through CLK3A/B), provided the VCO frequency remains within Fvco/4 and Fvco/6 constraints for frequencies above 350 MHz. The SI5338F-B04078-GM maintains 0.7 ps RMS jitter even at these high frequencies when driven by a low-noise differential reference.

Does SI5338F-B04078-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338F-B04078-GM is explicitly validated for PCIe Gen 4 SRNS operation with a typical RMS jitter of 0.11–0.32 ps under specified conditions (PLL bandwidth 2–5 MHz, CDR = 10 MHz). This compliance is documented in Table 12 of the datasheet and confirmed using the Skyworks PCIe Clock Jitter Tool. The SI5338F-B04078-GM achieves this via its low-noise MultiSynth™ architecture and configurable loop filter settings.

Can SI5338F-B04078-GM generate different output voltages on each of its four output banks?

Yes, SI5338F-B04078-GM provides independent VDDO0 through VDDO3 supplies, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V concurrently. This enables direct interfacing with mixed-voltage devices-such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V legacy logic-without external level shifters. The SI5338F-B04078-GM datasheet specifies VDDOn tolerance as 1.4–3.63 V per rail.

Is an external crystal required for SI5338F-B04078-GM operation?

No, an external crystal is optional. SI5338F-B04078-GM accepts multiple reference sources: 8–30 MHz crystals (on IN1/IN2), 5–200 MHz CMOS clocks (on IN3/IN4), or 5–710 MHz differential inputs (on IN1/IN2 or IN5/IN6). Crystal operation requires proper load capacitance matching (17–19 pF recommended); however, the SI5338F-B04078-GM can also run from a clean system clock or recovered data clock without any crystal.

How is SI5338F-B04078-GM programmed, and is configuration retained after power cycle?

SI5338F-B04078-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates register maps and validates configurations. Configuration is stored in one-time-programmable (OTP) NVM, so the SI5338F-B04078-GM powers up with user-defined settings without host intervention. Factory-programmed units ship with pre-loaded configurations; field updates are supported via I²C writes during operation.