Skyworks Solutions Inc. SI5338F-B04216-GMR
- Part No.:
- SI5338F-B04216-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338F-B04216-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,547
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Product details
Overview
SI5338F-B04216-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA systems.
For engineers reviewing the SI5338F-B04216-GMR datasheet, SI5338F-B04216-GMR pinout, SI5338F-B04216-GMR application, or SI5338F-B04216-GMR equivalent, key selection criteria include its 4-output flexibility, 0 ppm synthesis accuracy, 1.8–3.3 V core supply, 24-QFN package, and PCIe Gen 3 SRNS compliance - all critical for high-reliability embedded timing designs.
Technical Context
The SI5338F-B04216-GMR integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) feeding a fractional-N MultiSynth™ synthesis engine per output. Each of the four outputs features independent R-divider, M-divider, and P-divider control, enabling true any-frequency generation from 0.16 MHz to 710 MHz.
It supports simultaneous differential (LVPECL/LVDS/HCSL/CML) and single-ended (CMOS/SSTL/HSTL) outputs with per-driver voltage selection (1.5/1.8/2.5/3.3 V), programmable phase offset (<20 ps steps), and glitchless frequency increment/decrement in 1 ppm steps - all configured via I²C/SMBus interface with ClockBuilder Pro software.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | Four independent clock outputs (CLK0A/B through CLK3A/B) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and GbE jitter requirements |
| Frequency range | 0.16–710 MHz per output, with integer/fractional synthesis and <1 ppb resolution |
| Input reference | Supports 8–30 MHz crystal, or 5–710 MHz differential/CMOS/SSTL/HSTL inputs |
| Supply voltage | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V |
| Operating temperature | –40 °C to +85 °C, qualified for industrial and telecom infrastructure environments |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338F-B04216-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair 1 | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended input pair | Supports 5–200 MHz CMOS-level input; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential clock outputs | Four fully independent output pairs; each configurable as LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output bank for mixed-voltage signaling |
| VDD | Core supply | 1.8/2.5/3.3 V ±10% core power; PSRR optimized for clean timing operation |
| SCL, SDA | I²C/SMBus interface | Standard two-wire serial programming; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal alarms |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis per output | Enables independent, zero-ppm-accuracy frequency generation on all four outputs without shared dividers |
| PCIe Gen 3 SRNS compliance | Meets 0.11–0.32 ps RMS jitter requirement under separate-reference-no-spread conditions |
| Programmable phase adjustment | ±45 ns range in <20 ps steps per output, enabling precise skew alignment in multi-clock domains |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled or I²C-initiated increment/decrement, no output interruption |
| Flexible spread spectrum | Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, for EMI reduction |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator supplying common-clock-mode references with sub-0.45 ps RMS jitter to meet PCIe Gen 4 CEM spec. Use Value: Eliminates need for four discrete oscillators while maintaining Gen 4 jitter compliance and enabling dynamic frequency margining. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering three distinct Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board space versus discrete XO solutions; supports IEEE 802.3 clause 49 jitter limits. |
| FPGA & ASIC Clocking | Telecom Line Card Sync |
Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR interface clock, and 100 MHz logic clock to a Xilinx Versal ACAP in a 5G baseband unit. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails (1.8 V, 2.5 V, 3.3 V) matching diverse FPGA I/O standards. Use Value: Enables single-device clock tree with matched skew and low additive jitter, simplifying timing closure. |
Use Scenario: Delivering synchronous 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and OTN mappers on a telecom line card. IC Role / Device Role / Timing Role: Precision timing IC supporting OC-12/STM-4 compliant jitter (≤0.7 ps RMS) and ITU-T G.823/G.8262 holdover stability. Use Value: Replaces legacy clock trees with single-chip solution meeting stratum-3E and syncE requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06189-GM | Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), but only two outputs | Best for dual-output, ultra-low-jitter applications where crystal integration reduces layout complexity | Select when needing <0.4 ps RMS jitter and crystal integration outweighs output count reduction |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS generator; no I²C interface or MultiSynth capability | Suitable only for static clock trees with known, unchanging frequencies | Choose only if design requires no runtime reconfiguration and uses only LVDS outputs at standard frequencies |
Compared with Si5332A-D06189-GM and ICS8430I-01T, the SI5338F-B04216-GMR uniquely balances four independent programmable outputs, PCIe Gen 4 compliance, and field-configurable jitter performance - making it optimal for complex, multi-standard timing architectures requiring post-deployment flexibility.
Availability
SI5338F-B04216-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338F-B04216-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock innovation.
The Si5338 product line was designed for high-density, multi-protocol timing in networking, computing, and telecom equipment - delivering programmable precision where discrete oscillators or fixed-function clock ICs fall short.
FAQ
What is the maximum output frequency supported by SI5338F-B04216-GMR?
The SI5338F-B04216-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL - with only two unique frequencies above 350 MHz simultaneously allowed (Fvco/4 and Fvco/6). This is confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6.
Does SI5338F-B04216-GMR support PCIe Gen 4 Common Clock mode?
Yes, SI5338F-B04216-GMR meets PCIe Gen 4 Common Clock jitter requirements (0.15–0.45 ps RMS, 10 kHz–50 MHz) per Table 12 of the datasheet, provided PLL bandwidth is set to 2–4 MHz and CDR is 10 MHz - verified using the Skyworks PCIe Clock Jitter Tool.
Can SI5338F-B04216-GMR generate different output voltages on each driver?
Yes, SI5338F-B04216-GMR provides independent VDDO0–VDDO3 pins, allowing each of the four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enabling mixed-signal interfaces (e.g., LVDS at 2.5 V and CMOS at 1.8 V) without level shifters.
Is an external crystal required for SI5338F-B04216-GMR operation?
No - SI5338F-B04216-GMR accepts multiple reference sources: 8–30 MHz crystal (on IN1/IN2), or external CMOS/SSTL/HSTL/differential clocks from 5–710 MHz. Crystal is optional; the device operates in free-running or buffered modes without it.
How is SI5338F-B04216-GMR programmed in-system?
SI5338F-B04216-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates register maps and configuration files. Configuration can be stored in on-chip OTP memory for autonomous startup.
SI5338F-B04216-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338F-B04216-GMR FAQ
1.How can I place an order for SI5338F-B04216-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338F-B04216-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338F-B04216-GMR reliable?
The price and inventory of SI5338F-B04216-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338F-B04216-GMR is usually 5 days.
3.What payment methods are accepted for SI5338F-B04216-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338F-B04216-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338F-B04216-GMR?
SI5338F-B04216-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338F-B04216-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338F-B04216-GMR?
For technical support, including SI5338F-B04216-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338F-B04216-GMR requirements.
6.How does Aetrix verify that SI5338F-B04216-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338F-B04216-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338F-B04216-GMR meets industry standards.
7.What is the process for return or replacement of SI5338F-B04216-GMR?
All SI5338F-B04216-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338F-B04216-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338F-B04216-GMR part is unused and in its original packaging.
Return procedure for SI5338F-B04216-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338F-B04216-GMR Tags

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