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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338F-B04371-GM

Name: SI5338F-B04371-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338F-B04371-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338F-B04371-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338F-B04371-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338F-B04371-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom and FPGA applications.

For engineers reviewing the SI5338F-B04371-GM datasheet, SI5338F-B04371-GM pinout, SI5338F-B04371-GM application, or SI5338F-B04371-GM equivalent, this page provides verified technical context, exact pin functions, real-world application mappings, and validated alternative options for high-speed serial interface clocking, processor/FPGA synchronization, and jitter-critical timing systems.

Technical Context

The SI5338F-B04371-GM integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) feeds a fractional-N MultiSynth™ synthesis engine per output, enabling independent integer/fractional frequency generation with <20 ps phase step resolution and 1 ppm frequency increment/decrement capability.

Its output stage supports per-driver voltage selection (1.5/1.8/2.5/3.3 V), spread-spectrum modulation (0.5–5.0% at 33–63 kHz), loss-of-lock/loss-of-signal alarms, and configurable buffer modes-including zero-delay external feedback-making it suitable for PCIe Common Clock, SRNS-compliant Gen 3, and multi-protocol timing consolidation.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and GbE jitter requirements without external cleanup.
Output Count & Type	Four differential outputs (CLK0A/B–CLK3A/B); supports up to eight single-ended clocks via configuration.
Frequency Range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply & Power	Single 1.8/2.5/3.3 V core supply; 45 mA typical core current at 100 MHz on all outputs with 25 MHz refclk.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range.
I²C Interface	SMBus-compatible; supports standard/fast-mode (100/400 kHz); enables full register configuration and status readback.

Pinout & Package

SI5338F-B04371-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential Input Pair 1	Accepts AC-coupled differential clock (5–710 MHz); requires external 100 Ω termination.
IN3, IN4	Single-Ended Input Pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
IN5, IN6	Differential Input Pair 2	Second AC-coupled differential input (5–710 MHz); identical electrical specs to IN1/IN2.
CLK0A, CLK0B	Differential Output 0	LVPECL/LVDS/HCSL/CML configurable; VDDO0 supplies output driver (1.4–3.63 V).
CLK1A, CLK1B	Differential Output 1	Independent format/voltage control via VDDO1; supports same frequency ranges as CLK0.
CLK2A, CLK2B	Differential Output 2	Configurable per-output; supports phase adjustment <20 ps steps and glitchless frequency tuning.
CLK3A, CLK3B	Differential Output 3	Final output pair; enables independent SSC, enable/disable (OEB), and phase offset programming.
SCL, SDA	I²C Serial Interface	Standard bidirectional bus; pull-up required; supports device configuration and status monitoring.
INTR	Interrupt Output	Open-drain alarm signal indicating loss-of-lock, loss-of-signal, or other fault conditions.
VDD, VDDO0–VDDO3	Power Supplies	VDD = core (1.8/2.5/3.3 V); VDDOx = per-output buffer supply (1.4–3.63 V), enabling mixed-voltage operation.
GND, RSVD_GND	Ground Terminals	Multiple dedicated ground pins including reserved ground (Pin 21) for noise isolation and thermal management.

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy per output, eliminating need for multiple crystals.
PCIe Gen 1–4 Compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS); validated with Intel Clock Jitter Tool.
Per-Output Voltage Control	VDDO0–VDDO3 allow mixed-signal designs: e.g., 1.8 V LVDS for FPGA, 3.3 V CMOS for microcontroller, simultaneously.
Glitchless Frequency Tuning	1 ppm-step frequency increment/decrement via pin or I²C, with update time ≤667 ns above 18 MHz.
Programmable Phase Offset	±45 ns range with <20 ps step resolution per output-enables precise skew alignment in multi-lane SerDes systems.
Spread Spectrum Clocking	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate-reduces EMI without affecting timing margin.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.15 ps RMS) clocks meeting PCIe Gen 4 Common Clock spec. Use Value: Eliminates four discrete oscillators; reduces board area by >60%; maintains sub-1 ps RMS jitter under simultaneous load.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a carrier-grade router line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates with <0.7 ps RMS jitter on LVDS outputs. Use Value: Replaces three separate XOs; supports dynamic reconfiguration via I²C during firmware updates without hardware change.
FPGA & Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying 200 MHz system clock, 100 MHz DDR interface clock, and 50 MHz debug clock to a Xilinx Versal ACAP in broadcast infrastructure equipment. IC Role / Device Role / Timing Role: Configurable quad clock source with independent CMOS/LVDS outputs and per-output voltage control (1.8 V/2.5 V/3.3 V). Use Value: Enables single-chip clock tree for heterogeneous SoC interfaces; avoids level-shifting components and layout complexity.	Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to SDI transceivers and frame synchronizers. IC Role / Device Role / Timing Role: Low-phase-noise generator supporting HCSL and LVDS outputs with <10 ps pk-pk period jitter at 148.5 MHz. Use Value: Meets broadcast-grade jitter limits (<0.2 UI) without external jitter cleaners; simplifies compliance testing.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.15 ps RMS) clocks meeting PCIe Gen 4 Common Clock spec.

Use Value: Eliminates four discrete oscillators; reduces board area by >60%; maintains sub-1 ps RMS jitter under simultaneous load.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a carrier-grade router line card.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates with <0.7 ps RMS jitter on LVDS outputs.

Use Value: Replaces three separate XOs; supports dynamic reconfiguration via I²C during firmware updates without hardware change.

FPGA & Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying 200 MHz system clock, 100 MHz DDR interface clock, and 50 MHz debug clock to a Xilinx Versal ACAP in broadcast infrastructure equipment.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent CMOS/LVDS outputs and per-output voltage control (1.8 V/2.5 V/3.3 V).

Use Value: Enables single-chip clock tree for heterogeneous SoC interfaces; avoids level-shifting components and layout complexity.

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to SDI transceivers and frame synchronizers.

IC Role / Device Role / Timing Role: Low-phase-noise generator supporting HCSL and LVDS outputs with <10 ps pk-pk period jitter at 148.5 MHz.

Use Value: Meets broadcast-grade jitter limits (<0.2 UI) without external jitter cleaners; simplifies compliance testing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06181-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), but larger 32-QFN package.	Preferred for new designs requiring >4 outputs or factory pre-programming; not drop-in due to pin count and footprint change.	Select when scalability and ultra-low jitter outweigh cost and board space constraints.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; 3.3 V only; no spread spectrum.	Suitable only for static clock trees where frequencies never change; lacks flexibility for multi-protocol or field-upgradable systems.	Choose only for cost-sensitive, fixed-clock applications with no requirement for reconfiguration or mixed-voltage outputs.

Compared with Si5332A-D06181-GM, SI5338F-B04371-GM offers smaller footprint and lower BOM cost for 4-output needs; versus ICS8430I-01T, it delivers field-programmability, voltage flexibility, and PCIe Gen 4 compliance-critical for adaptive timing architectures.

Availability

SI5338F-B04371-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338F-B04371-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems-targeting PCIe, Ethernet, telecom, and broadcast video where jitter, flexibility, and integration are critical.

FAQ

What is the maximum output frequency supported by SI5338F-B04371-GM in LVPECL mode?

The SI5338F-B04371-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6. This applies when using differential outputs with appropriate termination and supply voltage (VDDO ≥ 2.375 V for LVPECL). Frequencies above 350 MHz require use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique values.

Does SI5338F-B04371-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338F-B04371-GM is explicitly validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (Table 12), measured per PCI-SIG specifications using the Skyworks PCIe Clock Jitter Tool. It meets the jitter mask for 100 MHz HCSL outputs with PLL bandwidth set to 2–4 MHz and CDR = 10 MHz.

Can SI5338F-B04371-GM generate different output voltages simultaneously?

Yes, SI5338F-B04371-GM supports independent output supply rails: VDDO0 through VDDO3 each drive one differential output pair and can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows concurrent LVDS (1.8 V), HCSL (3.3 V), and CMOS (2.5 V) outputs without level shifters-verified in Table 3 and Section 3.4 of the datasheet.

What is the minimum input clock frequency supported in PLL bypass (buffer) mode for SI5338F-B04371-GM?

In PLL bypass mode, SI5338F-B04371-GM supports input frequencies down to 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is only functional above 5 MHz-per Table 5 note 3 and Section 3.2 of the datasheet.

How is phase alignment controlled across the four outputs of SI5338F-B04371-GM?

SI5338F-B04371-GM provides independent programmable phase offset per output with ±45 ns range and <20 ps step resolution (Table 5). Phase is adjusted digitally via I²C or pin control (PINC/FDEC), enabling precise skew calibration between SerDes lanes or memory interfaces without external delay lines.

SI5338F-B04371-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338F-B04371-GM FAQ

1.How can I place an order for SI5338F-B04371-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338F-B04371-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338F-B04371-GM reliable?

The price and inventory of SI5338F-B04371-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338F-B04371-GM is usually 5 days.

3.What payment methods are accepted for SI5338F-B04371-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338F-B04371-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338F-B04371-GM?

SI5338F-B04371-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338F-B04371-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338F-B04371-GM?

For technical support, including SI5338F-B04371-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338F-B04371-GM requirements.

6.How does Aetrix verify that SI5338F-B04371-GM is sourced from the original manufacturer or authorized distributors?

All SI5338F-B04371-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338F-B04371-GM meets industry standards.

7.What is the process for return or replacement of SI5338F-B04371-GM?

All SI5338F-B04371-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338F-B04371-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338F-B04371-GM part is unused and in its original packaging.

Return procedure for SI5338F-B04371-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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