Skyworks Solutions Inc. SI5338F-B04385-GMR

Overview

SI5338F-B04385-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for input frequencies up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338F-B04385-GMR datasheet, SI5338F-B04385-GMR pinout, SI5338F-B04385-GMR application, or SI5338F-B04385-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus configuration interface.

Technical Context

The SI5338F-B04385-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports programmable phase offset (<20 ps step), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate).

It operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and independent output buffer supplies (VDDO0–VDDO3) ranging from 1.4 V to 3.63 V. Loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and glitchless frequency adjustment via dedicated pins (PINC/FINC) are integrated for system-level timing robustness.

Key Specifications

Pinout & Package

SI5338F-B04385-GMR is housed in a 24-pin, 4 × 4 mm, 0.5 mm pitch QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports standard reflow profiles per JEDEC J-STD-020 and provides low thermal resistance (θ_JA = 37 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D06983-GM, SI5338F-B04385-GMR offers broader frequency coverage and external crystal flexibility but trades off integrated timing stability; versus ICS8430I-01LG, it delivers full configurability and PCIe Gen 4 readiness at higher design complexity and cost.

Availability

SI5338F-B04385-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, FPGA-based telecom line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for SI5338F-B04385-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing expertise.

The Si5338 family was designed specifically for high-speed serial interface timing-replacing multiple oscillators in PCIe, Ethernet, Fibre Channel, and broadcast systems while delivering sub-picosecond jitter and field-programmable flexibility.

FAQ

What is the maximum output frequency supported by SI5338F-B04385-GMR?

The SI5338F-B04385-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. Two unique frequencies above 350 MHz (e.g., Fvco/4 and Fvco/6) can be generated simultaneously. All frequencies are synthesized with MultiSynth™ technology and maintain 0.7 ps RMS typical jitter.

Does SI5338F-B04385-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338F-B04385-GMR meets PCIe Gen 4 Common Clock jitter specifications (≤0.45 ps RMS, 10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL 100 MHz outputs and recommended PLL bandwidth (2–4 MHz). Measurement validation is confirmed using the Skyworks PCIe Clock Jitter Tool.

How is SI5338F-B04385-GMR programmed and configured?

SI5338F-B04385-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output format, frequency, voltage, phase offset, spread spectrum, and alarm settings. Factory-programmed NVM allows standalone boot without host processor involvement.

Can SI5338F-B04385-GMR operate in clock buffer (PLL bypass) mode?

Yes, SI5338F-B04385-GMR supports clock buffer mode with additive phase jitter as low as 0.165 ps RMS (12 kHz–20 MHz). In this mode, input clocks pass directly to outputs with minimal latency (2.5–4 ns propagation delay) and retain loss-of-signal detection functionality for monitoring reference integrity.

What are the thermal characteristics and power consumption of SI5338F-B04385-GMR?

SI5338F-B04385-GMR has θ_JA = 37 °C/W and θ_JC = 10 °C/W. Core supply current is 45 mA typical (100 MHz on all outputs, 25 MHz refclk); output buffer current varies by format and frequency (e.g., 30 mA max for LVPECL at 710 MHz). Total power dissipation remains under 1.2 W at full load and 85 °C ambient.