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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338G-B-GMR

Name: SI5338G-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338G-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338G-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338G-B-GMR.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338G-B-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338G-B-GMR datasheet, SI5338G-B-GMR pinout, SI5338G-B-GMR application, or SI5338G-B-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet switch use cases, and two technically documented alternative parts with explicit functional and application-level differences.

Technical Context

The SI5338G-B-GMR integrates a fractional-N PLL with patented MultiSynth™ synthesis stages per output, enabling independent any-frequency generation (0.16–710 MHz) without external loop filters. Its dual-stage architecture separates reference conditioning (Stage 1) from output-specific frequency/phase/spread-spectrum control (Stage 2), supporting simultaneous integer and fractional synthesis modes.

It accepts six input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential - and provides loss-of-lock and loss-of-signal alarms. Each output driver supports independent voltage (1.5/1.8/2.5/3.3 V), format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and spread-spectrum modulation (0.5–5.0%, 33–63 kHz).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps)
Output Frequency Range	0.16–710 MHz per channel; supports Fvco/4 and Fvco/6 for >350 MHz outputs
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: 1.4–3.63 V independently configurable
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, lead-free, halogen-free
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz refclk

Pinout & Package

SI5338G-B-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants per Skyworks documentation (Rev. 1.6, p.33–37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each configurable for format, voltage, and slew
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage selection (1.5/1.8/2.5/3.3 V); decoupling required per pin
VDD	Core supply	1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal for loss-of-lock and loss-of-signal alarms
RSVD_GND	Reserved ground	Internal no-connect; must be tied to GND per layout guidelines

Key Features

Feature	Design Value
Independent output frequency synthesis	Each of four outputs generates any frequency (0.16–710 MHz) with true zero ppm accuracy using MultiSynth™
Glitchless frequency adjustment	1 ppm step size via PINC/FDEC pins; update time ≤667 ns for outputs >18 MHz
Programmable phase offset	±45 ns range with <20 ps step resolution per output; enables skew compensation in multi-lane systems
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI in dense PCB layouts
PCIe Gen 4 compliance	Meets 0.15–0.45 ps RMS jitter requirement under common clock architecture with 2–5 MHz PLL bandwidth

Applications

Ethernet Switch/Routing Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-density 10GbE/25GbE switch fabric requiring synchronized clocks across multiple PHYs and MACs. IC Role / Device Role / Timing Role: Primary clock generator providing four independent, low-jitter clocks (e.g., 156.25 MHz, 312.5 MHz, 625 MHz, 1.25 GHz divided) to SerDes lanes and packet processors. Use Value: Eliminates four discrete XO sources while maintaining sub-0.45 ps RMS jitter required for PCIe Gen 4 and IEEE 802.3bj KR/KP compliance.	Use Scenario: Server motherboard with multiple PCIe slots (x16/x8/x4) and CPU/U.2 NVMe controllers sharing a common reference. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz HCSL to root complex and endpoints; supports SRNS mode for Gen 3 and common clock for Gen 4. Use Value: Meets PCIe Base Spec 4.0 jitter limits (≤0.45 ps RMS) and enables deterministic inter-lane skew control via per-output phase adjustment.
Broadcast Video/Audio Synchronization	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2082/ST 2081 video over IP gateway requiring precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight phase alignment. IC Role / Device Role / Timing Role: Quad-output generator synthesizing exact video frequencies from a single 27 MHz crystal; uses independent phase offsets to align frame boundaries. Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter-critical for multi-link 4K/8K video transport without frame tearing.	Use Scenario: Heterogeneous SoC/FPGA platform with ARM cores, DDR4 memory, PCIe, and Gigabit Ethernet subsystems needing isolated, voltage-matched clocks. IC Role / Device Role / Timing Role: Central timing hub delivering 1 GHz processor clock (HCSL), 1333 MHz DDR4 clock (SSTL), 125 MHz Ethernet (LVDS), and 100 MHz PCIe (HCSL) from one device. Use Value: Reduces BOM count by 75% vs. discrete oscillators; independent VDDO pins allow 1.8 V DDR4 and 3.3 V Ethernet clocks simultaneously.

Ethernet Switch/Routing Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-density 10GbE/25GbE switch fabric requiring synchronized clocks across multiple PHYs and MACs.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent, low-jitter clocks (e.g., 156.25 MHz, 312.5 MHz, 625 MHz, 1.25 GHz divided) to SerDes lanes and packet processors.

Use Value: Eliminates four discrete XO sources while maintaining sub-0.45 ps RMS jitter required for PCIe Gen 4 and IEEE 802.3bj KR/KP compliance.

Use Scenario: Server motherboard with multiple PCIe slots (x16/x8/x4) and CPU/U.2 NVMe controllers sharing a common reference.

IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz HCSL to root complex and endpoints; supports SRNS mode for Gen 3 and common clock for Gen 4.

Use Value: Meets PCIe Base Spec 4.0 jitter limits (≤0.45 ps RMS) and enables deterministic inter-lane skew control via per-output phase adjustment.

Broadcast Video/Audio Synchronization

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2082/ST 2081 video over IP gateway requiring precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight phase alignment.

IC Role / Device Role / Timing Role: Quad-output generator synthesizing exact video frequencies from a single 27 MHz crystal; uses independent phase offsets to align frame boundaries.

Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter-critical for multi-link 4K/8K video transport without frame tearing.

Use Scenario: Heterogeneous SoC/FPGA platform with ARM cores, DDR4 memory, PCIe, and Gigabit Ethernet subsystems needing isolated, voltage-matched clocks.

IC Role / Device Role / Timing Role: Central timing hub delivering 1 GHz processor clock (HCSL), 1333 MHz DDR4 clock (SSTL), 125 MHz Ethernet (LVDS), and 100 MHz PCIe (HCSL) from one device.

Use Value: Reduces BOM count by 75% vs. discrete oscillators; independent VDDO pins allow 1.8 V DDR4 and 3.3 V Ethernet clocks simultaneously.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance	Targeted at ultra-low-jitter 100G/400G optical modules and AI accelerator cards where <0.4 ps RMS is mandatory	Select when system demands <0.4 ps RMS jitter and ≥8 outputs; not drop-in due to different pinout, higher cost, and added complexity
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 0.1–700 MHz range; 3.3 V only	Used in cost-sensitive, static-clocking applications like legacy storage controllers where frequency flexibility is unnecessary	Select only for non-programmable, fixed-frequency deployments; lacks spread spectrum, phase adjustment, and multi-voltage support of SI5338G-B-GMR

Compared with Si5332A-D-GM, SI5338G-B-GMR offers lower system cost and simpler layout but trades 0.35 ps RMS jitter for broader configurability; compared with ICS8430I-01LG, it adds full I²C programmability and voltage/format flexibility at the cost of higher design effort and BOM cost.

Availability

SI5338G-B-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 add-in cards, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338G-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise frequency synthesis and deterministic phase control are critical.

FAQ

What is the maximum output frequency supported by SI5338G-B-GMR?

The SI5338G-B-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be generated simultaneously-Fvco/4 and Fvco/6-as specified in Skyworks Rev. 1.6 datasheet Section 3.3.

Does SI5338G-B-GMR support PCIe Gen 4 Common Clock architecture?

Yes, SI5338G-B-GMR is explicitly compliant with PCIe Gen 4 Common Clock requirements, delivering ≤0.45 ps RMS jitter (typical 0.15 ps) at 100 MHz HCSL output under 2–5 MHz PLL bandwidth conditions, as verified in Table 12 of the Skyworks datasheet Rev. 1.6.

Can SI5338G-B-GMR generate different output voltages on each channel?

Yes, SI5338G-B-GMR provides independent VDDO0–VDDO3 pins, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V-enabling direct interfacing with mixed-voltage systems such as DDR4 (1.2 V SSTL), Ethernet PHYs (3.3 V CMOS), and FPGA banks (1.8 V LVDS).

How is SI5338G-B-GMR programmed, and what tools are required?

SI5338G-B-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which auto-generates configuration files and register maps based on user-defined frequency, format, and jitter requirements. No external hardware programmer is needed-only a USB-to-I²C adapter and the free ClockBuilder Pro GUI.

What is the thermal performance of SI5338G-B-GMR in continuous operation?

SI5338G-B-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air. At 45 mA typical core current and 3.3 V supply, power dissipation is ~149 mW, resulting in <6 °C junction-to-ambient rise-well within the –40 °C to +85 °C operating range without forced airflow or heatsinking.

SI5338G-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 710MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338G-B-GMR FAQ

1.How can I place an order for SI5338G-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338G-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338G-B-GMR reliable?

The price and inventory of SI5338G-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338G-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5338G-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338G-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338G-B-GMR?

SI5338G-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338G-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338G-B-GMR?

For technical support, including SI5338G-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338G-B-GMR requirements.

6.How does Aetrix verify that SI5338G-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338G-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338G-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5338G-B-GMR?

All SI5338G-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338G-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338G-B-GMR part is unused and in its original packaging.

Return procedure for SI5338G-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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