Skyworks Solutions Inc. SI5338H-B04835-GMR

Overview

SI5338H-B04835-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed networking and FPGA clocking systems.

For engineers reviewing the SI5338H-B04835-GMR datasheet, SI5338H-B04835-GMR pinout, SI5338H-B04835-GMR application, or SI5338H-B04835-GMR equivalent, this page delivers verified technical context, exact pin functions, PCIe-validated jitter performance, output voltage configurability per driver (1.5/1.8/2.5/3.3 V), and confirmed alternative options for multi-frequency timing designs.

Technical Context

The SI5338H-B04835-GMR implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2. Each output driver operates with its own M/N/R divider set, enabling true zero-ppm frequency accuracy on all four outputs simultaneously.

It supports glitchless real-time frequency adjustment in 1 ppm steps and phase tuning in <20 ps increments per output, with independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation rate) on any output. Loss-of-lock and loss-of-signal alarms are provided via the INTR pin, and external feedback enables zero-delay mode.

Key Specifications

Pinout & Package

SI5338H-B04835-GMR is housed in a 24-pin, 4 mm × 4 mm, 0.5 mm pitch QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin numbering proceeds counterclockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D06889-GM and ICS853S01AGI-01LFT, SI5338H-B04835-GMR uniquely balances programmable synthesis, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for space-constrained, multi-protocol systems requiring both flexibility and validation.

Availability

SI5338H-B04835-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338H-B04835-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems-delivering programmable any-frequency synthesis with industry-leading jitter performance in minimal footprint.

FAQ

What input reference frequencies does the SI5338H-B04835-GMR support?

The SI5338H-B04835-GMR supports six input types: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). It accepts both single-ended (IN3/IN4) and dual differential pairs (IN1/IN2, IN5/IN6), enabling flexible system-level clock tree design without external translators. SI5338H-B04835-GMR uses internal termination and slew-rate optimization to maintain jitter integrity across all input modes.

Does the SI5338H-B04835-GMR meet PCIe Gen 4 timing requirements?

Yes, the SI5338H-B04835-GMR is validated for PCIe Gen 4 Common Clock mode with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz), compliant with PCI-SIG Base Specification 4.0 rev 0.5. It also meets PCIe Gen 3 SRNS requirements (0.11–0.32 ps RMS) and includes dedicated jitter measurement support via Skyworks' free PCIe Clock Jitter Tool. SI5338H-B04835-GMR achieves this using its low-noise PLL architecture and optimized MultiSynth™ stage.

Can all four outputs of the SI5338H-B04835-GMR operate at different frequencies and signal formats simultaneously?

Yes, SI5338H-B04835-GMR supports fully independent configuration per output: each of CLK0–CLK3 can be set to distinct frequencies (0.16–710 MHz), formats (LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL), and supply voltages (1.5/1.8/2.5/3.3 V via VDDO0–VDDO3). This enables mixed-interface systems-e.g., LVDS for FPGA, HCSL for CPU, CMOS for microcontroller-all from one device. SI5338H-B04835-GMR's per-output registers ensure no functional crosstalk.

How is the SI5338H-B04835-GMR programmed, and is configuration persistent?

The SI5338H-B04835-GMR is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which auto-generates register maps and validates configurations. Configuration is stored in one-time-programmable (OTP) memory; once written, SI5338H-B04835-GMR boots with pre-programmed settings and delivers valid clocks within 2 ms of power-on. Field updates remain possible via I²C without OTP rewrite.

What thermal and power specifications apply to the SI5338H-B04835-GMR?

SI5338H-B04835-GMR operates from –40 °C to +85 °C ambient, with junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air. Core supply current is 45 mA typical at 100 MHz on all outputs with 25 MHz reference; output buffer current varies by format and frequency (e.g., 30 mA max for LVPECL at 710 MHz). SI5338H-B04835-GMR includes robust PSRR and on-chip thermal monitoring logic.