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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338H-B-GM

Name: SI5338H-B-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338H-B-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338H-B-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338H-B-GM.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338H-B-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338H-B-GM datasheet, SI5338H-B-GM pinout, SI5338H-B-GM application, or SI5338H-B-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), flexible reference inputs (crystal, CMOS, SSTL/HSTL, differential), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338H-B-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to an external reference, followed by four independent fractional-N MultiSynth™ synthesizers (Stage 2) generating each output. This enables true zero-ppm frequency accuracy and independent phase/frequency adjustment per output.

Each output driver supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL formats with per-channel VDDO supply (1.5–3.3 V), while the core operates from a single 1.8/2.5/3.3 V supply. Input options include 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential signals.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); enables flexible system clock sourcing.
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver - simplifies mixed-voltage board design.
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments without derating.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; surface-mount compatible with standard reflow profiles and IPC-7351B land pattern.
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference - enables low-power timing in dense systems.

Pinout & Package

SI5338H-B-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.6 datasheet (page 37), supporting I²C configuration, six input references (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), four independent VDDO supplies, interrupt signaling (INTR), and power/ground distribution.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled 5–710 MHz differential clocks; require external 100 Ω termination for optimal jitter performance.
IN3, IN4	Single-ended clock inputs	Support DC-coupled CMOS/SSTL/HSTL inputs (5–350 MHz); slew rate >1 V/ns recommended for low jitter.
CLK0A–CLK3B (x4 pairs)	Differential clock outputs	Each pair delivers independently synthesized frequency/format; LVPECL/LVDS/HCSL/CML selectable per channel.
VDDO0–VDDO3	Output buffer supply rails	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) - eliminates level-shifting components for mixed-signal SoCs/FPGAs.
SCL, SDA	I²C/SMBus interface	Standard 2-wire serial bus (up to 400 kHz) for register programming, status readback, and dynamic frequency/phase tuning.
INTR	Interrupt output	Open-drain signal indicating loss-of-lock or loss-of-signal events - enables real-time fault monitoring without polling.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver any-frequency outputs (0.16–710 MHz) with 0 ppm precision - eliminates need for multiple crystals or discrete PLLs.
Independent phase adjustment	±45 ns range in <20 ps steps per output - enables precise skew alignment between processor, memory, and peripheral clocks.
Spread spectrum clocking (SSC)	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency - reduces EMI without altering system timing margins.
Glitchless frequency tuning	1 ppm increment/decrement via pin or I²C - allows real-time clock rate adaptation during system operation (e.g., thermal throttling, power state transitions).
External feedback mode	Supports zero-delay operation by feeding back a system clock - maintains deterministic latency in synchronous timing architectures.

Applications

Ethernet Switch/Router Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with matched phase alignment and sub-ps jitter. Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting IEEE 802.3 jitter limits and enabling multi-rate port flexibility.	Use Scenario: Server motherboard with PCIe Gen 3/4 slots, CPU, and chipset requiring compliant common clock or SRNS timing. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz differential clocks with <0.32 ps RMS jitter (Gen 3 SRNS) and <0.45 ps RMS (Gen 4). Use Value: Passes Intel Clock Jitter Tool validation out-of-box; supports both common clock and separate reference topologies without hardware change.
Processor & FPGA Clock Distribution	Broadcast Video/Audio Timing
Use Scenario: Heterogeneous compute platform with ARM SoC, FPGA fabric, DDR4 memory, and video encoder-all needing distinct, phase-aligned clocks. IC Role / Device Role / Timing Role: Configurable clock generator supplying 50 MHz (SoC), 100 MHz (FPGA logic), 200 MHz (DDR4), and 27 MHz (encoder) from one device. Use Value: Reduces BOM count and PCB area; independent VDDO per output matches diverse I/O voltage requirements without external regulators.	Use Scenario: SMPTE 2110/2022-6 IP video router requiring genlock-capable, low-jitter reference clocks for frame synchronization. IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz with <10 ps pk-pk period jitter and programmable phase offset. Use Value: Meets SMPTE ST 2059-2 PTP grandmaster timing stability; supports seamless source switching via glitchless frequency/phase update.

Ethernet Switch/Router Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with matched phase alignment and sub-ps jitter.

Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting IEEE 802.3 jitter limits and enabling multi-rate port flexibility.

Use Scenario: Server motherboard with PCIe Gen 3/4 slots, CPU, and chipset requiring compliant common clock or SRNS timing.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz differential clocks with <0.32 ps RMS jitter (Gen 3 SRNS) and <0.45 ps RMS (Gen 4).

Use Value: Passes Intel Clock Jitter Tool validation out-of-box; supports both common clock and separate reference topologies without hardware change.

Processor & FPGA Clock Distribution

Broadcast Video/Audio Timing

Use Scenario: Heterogeneous compute platform with ARM SoC, FPGA fabric, DDR4 memory, and video encoder-all needing distinct, phase-aligned clocks.

IC Role / Device Role / Timing Role: Configurable clock generator supplying 50 MHz (SoC), 100 MHz (FPGA logic), 200 MHz (DDR4), and 27 MHz (encoder) from one device.

Use Value: Reduces BOM count and PCB area; independent VDDO per output matches diverse I/O voltage requirements without external regulators.

Use Scenario: SMPTE 2110/2022-6 IP video router requiring genlock-capable, low-jitter reference clocks for frame synchronization.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz with <10 ps pk-pk period jitter and programmable phase offset.

Use Value: Meets SMPTE ST 2059-2 PTP grandmaster timing stability; supports seamless source switching via glitchless frequency/phase update.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs; requires different footprint (32-QFN).	Better suited for space-constrained, ultra-low-jitter designs where crystal integration simplifies layout and improves reliability.	Select Si5332A-D-GM when board space is limited and jitter budget is tighter than 0.7 ps RMS; avoid if legacy 24-QFN footprint must be retained.
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment.	Applicable only in static clock trees where frequencies never change and jitter tolerance is relaxed.	Choose ICS8430I-01LG only for cost-sensitive, non-reconfigurable applications with fixed 100/125/156.25 MHz outputs and no phase control needs.

Compared with Si5332A-D-GM and ICS8430I-01LG, the SI5338H-B-GM uniquely balances field-programmability, jitter performance, and 24-QFN compatibility - making it optimal for mid-volume industrial and telecom designs requiring post-silicon clock tuning without footprint redesign.

Availability

SI5338H-B-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clocking, and processor/FPGA clock distribution requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338H-B-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and clock technology expertise.

The Si5338 family was designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems - emphasizing programmability, jitter performance, and integration of PCIe, Ethernet, and video timing standards into a single IC.

FAQ

What is the maximum output frequency supported by SI5338H-B-GM in LVPECL format?

The SI5338H-B-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability applies when using the MultiSynth™ synthesizer in integer mode and is validated for jitter performance under specified load and supply conditions. The SI5338H-B-GM achieves this while maintaining 0.7 ps RMS phase jitter, making it suitable for high-speed SerDes applications.

Does SI5338H-B-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338H-B-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) as specified in Table 12 of the Skyworks datasheet. This compliance is verified using the Intel Clock Jitter Tool and assumes HCSL 100 MHz outputs with appropriate PLL bandwidth configuration (2–4 or 2–5 MHz) and CDR = 10 MHz.

Can SI5338H-B-GM generate different output voltages on each channel?

Yes, the SI5338H-B-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This per-channel voltage control enables direct interfacing with mixed-voltage devices like 1.8 V FPGAs, 2.5 V ASICs, and 3.3 V legacy peripherals without external level shifters - a key feature confirmed in the "Features" section and Table 3 of the datasheet.

How is SI5338H-B-GM programmed, and what software is required?

The SI5338H-B-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates configuration files and supports real-time tuning of frequency, phase, spread spectrum, and output format. ClockBuilder Pro is freely available at skyworksinc.com and auto-generates register maps tailored to the SI5338H-B-GM's specific pinout and feature set.

What package type and dimensions does SI5338H-B-GM use?

The SI5338H-B-GM uses a 24-lead QFN package measuring 4 mm × 4 mm with 0.5 mm pitch and an exposed thermal pad, as documented in Section 9 ("Package Outline") of the Skyworks Rev. 1.6 datasheet. This compact footprint supports high-density PCB layouts and is compatible with standard reflow soldering processes per JEDEC J-STD-020.

SI5338H-B-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338H-B-GM FAQ

1.How can I place an order for SI5338H-B-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338H-B-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338H-B-GM reliable?

The price and inventory of SI5338H-B-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338H-B-GM is usually 5 days.

3.What payment methods are accepted for SI5338H-B-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338H-B-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338H-B-GM?

SI5338H-B-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338H-B-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338H-B-GM?

For technical support, including SI5338H-B-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338H-B-GM requirements.

6.How does Aetrix verify that SI5338H-B-GM is sourced from the original manufacturer or authorized distributors?

All SI5338H-B-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338H-B-GM meets industry standards.

7.What is the process for return or replacement of SI5338H-B-GM?

All SI5338H-B-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338H-B-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338H-B-GM part is unused and in its original packaging.

Return procedure for SI5338H-B-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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