Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338H-B-GMR

Name: SI5338H-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338H-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338H-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338H-B-GMR.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,166

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338H-B-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typical phase jitter), PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338H-B-GMR datasheet, SI5338H-B-GMR pinout, SI5338H-B-GMR application, or SI5338H-B-GMR equivalent, key selection criteria include its 24-QFN package, 1.8/2.5/3.3 V core supply, independent per-output voltage control (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, and <20 ps phase step resolution - all critical for FPGA, processor, and PCIe Gen 4 clocking designs.

Technical Context

The SI5338H-B-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a fractional-N MultiSynth™ VCO stage (Fvco = 4.85–5.67 GHz), enabling any-frequency synthesis with 1 ppb resolution. Each of the four output drivers operates independently with dedicated M/N/P dividers and configurable output format, voltage, and spread-spectrum parameters.

It supports six input sources - differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or external crystal (8–30 MHz) - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and I²C/SMBus-compatible configuration via OTP NVM or RAM runtime programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps)
Output Frequency Range	0.16–710 MHz per channel; supports simultaneous ≥350 MHz outputs only at Fvco/4 and Fvco/6
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Format Flexibility	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently configurable
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per driver (1.5/1.8/2.5/3.3 V supported)
Temperature Range	–40 °C to +85 °C; qualified for industrial embedded and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; RoHS-compliant, GMR suffix denotes green packaging

Pinout & Package

SI5338H-B-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk 1/2), IN5/IN6 (diff clk 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz; independent VDDO0 supply
CLK1A / CLK1B	Differential output pair 1	Independent format/voltage/frequency; same capability as CLK0; enables multi-protocol clock distribution
CLK2A / CLK2B	Differential output pair 2	Supports PCIe Gen 4 100 MHz HCSL or 156.25 MHz LVDS; SRNS-compliant when configured per spec
CLK3A / CLK3B	Differential output pair 3	Can be set to broadcast video timing (e.g., 74.25 MHz) while others serve CPU/FPGA domains
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz; internal 100 Ω termination; slew rate >0.3 V/ns required for optimal jitter
SCL / SDA	I²C serial interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; used with ClockBuilder Pro for configuration
INTR	Interrupt output	Open-drain status flag for loss-of-lock or loss-of-signal events; pulls low on alarm condition
VDDO0–VDDO3	Per-output buffer supplies	Enable mixed-voltage system clocking (e.g., 1.8 V FPGA + 3.3 V PHY) without level shifters

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs with true zero-ppm accuracy and 1 ppb frequency resolution per channel
Glitchless Frequency Adjustment	1 ppm step size with pin-controlled or I²C-initiated increment/decrement; no output interruption during update
Programmable Phase Offset	±45 ns range with <20 ps step resolution; enables precise skew management across SerDes lanes
Configurable Spread Spectrum	0.5–5.0% down-spread at 33–63 kHz modulation rate on any output; reduces EMI in dense PCB layouts
PCIe Gen 4 Compliance	Validated for Common Clock topology with ≤0.45 ps RMS jitter (10 kHz–50 MHz); supports SRNS mode per spec
External Feedback Mode	Enables zero-delay operation for clock forwarding applications; eliminates propagation delay between input and output

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter clocks meeting PCIe Gen 4 Common Clock RMS jitter limit (≤0.45 ps). Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane skew (<100 ps) and full Gen 4 link training reliability.	Use Scenario: Generating 156.25 MHz LVDS and 312.5 MHz HCSL clocks for 10 GbE MAC/PHY and packet processor in a Layer 3 switch. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed signal formats and voltages across Ethernet subsystems. Use Value: Reduces BOM count and layout area; enables dynamic frequency scaling for power-aware traffic shaping.
Broadcast Video Timing	FPGA & Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks (74.25 MHz, 148.5 MHz) and genlock signals to video encoder/decoder SoCs. IC Role / Device Role / Timing Role: Precision frequency translator generating exact broadcast-standard frequencies from a single crystal input. Use Value: Achieves sub-1 ps RMS jitter required for 4K/8K video integrity; avoids frame sync errors and color artifacts.	Use Scenario: Supplying 500 MHz LVDS to an FPGA transceiver bank and 1 GHz CMOS to an ARM-based application processor in an industrial controller. IC Role / Device Role / Timing Role: Multi-format, multi-voltage clock generator enabling heterogeneous SoC interfacing without external level translation. Use Value: Simplifies power domain partitioning; supports independent frequency scaling for compute vs. I/O subsystems.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter clocks meeting PCIe Gen 4 Common Clock RMS jitter limit (≤0.45 ps).

Use Value: Eliminates need for four discrete oscillators; ensures deterministic inter-lane skew (<100 ps) and full Gen 4 link training reliability.

Use Scenario: Generating 156.25 MHz LVDS and 312.5 MHz HCSL clocks for 10 GbE MAC/PHY and packet processor in a Layer 3 switch.

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed signal formats and voltages across Ethernet subsystems.

Use Value: Reduces BOM count and layout area; enables dynamic frequency scaling for power-aware traffic shaping.

Broadcast Video Timing

FPGA & Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks (74.25 MHz, 148.5 MHz) and genlock signals to video encoder/decoder SoCs.

IC Role / Device Role / Timing Role: Precision frequency translator generating exact broadcast-standard frequencies from a single crystal input.

Use Value: Achieves sub-1 ps RMS jitter required for 4K/8K video integrity; avoids frame sync errors and color artifacts.

Use Scenario: Supplying 500 MHz LVDS to an FPGA transceiver bank and 1 GHz CMOS to an ARM-based application processor in an industrial controller.

IC Role / Device Role / Timing Role: Multi-format, multi-voltage clock generator enabling heterogeneous SoC interfacing without external level translation.

Use Value: Simplifies power domain partitioning; supports independent frequency scaling for compute vs. I/O subsystems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 12 outputs via fanout; requires different footprint (32-QFN)	Better suited for space-constrained, ultra-low-jitter applications like optical transport; not drop-in compatible due to pinout and package change	Select Si5332A-D-GM if jitter budget is <0.4 ps RMS and board redesign is acceptable; SI5338H-B-GMR remains optimal for cost-sensitive, pin-compatible upgrades.
ICS854S01I	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; max output 700 MHz; jitter 1.2 ps RMS	Limited to static clock trees; lacks frequency flexibility, spread spectrum, or phase adjustment features	Choose ICS854S01I only for legacy designs requiring simple, low-cost clock fanout without reconfiguration needs.

Compared with Si5332A-D-GM and ICS854S01I, the SI5338H-B-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and 24-QFN footprint - making it the preferred choice for upgradeable, multi-protocol timing in industrial and telecom platforms where layout reuse and firmware-defined clocking are essential.

Availability

SI5338H-B-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338H-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing IP.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems - targeting PCIe, Ethernet, broadcast, and telecom applications where jitter, flexibility, and footprint efficiency are critical.

FAQ

What is the maximum output frequency supported by the SI5338H-B-GMR on a single channel?

The SI5338H-B-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated - specifically Fvco/4 and Fvco/6 - due to VCO bandwidth constraints. All outputs retain 0.7 ps RMS jitter performance within their respective format limits.

Does the SI5338H-B-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338H-B-GMR is compliant with PCIe Gen 4 SRNS requirements when configured with a PLL loop bandwidth of 2–4 MHz or 2–5 MHz and CDR = 10 MHz, achieving ≤0.32 ps RMS jitter (typical). This is validated per PCI Express Base Specification 4.0 rev. 0.5 and confirmed in Skyworks' AN562 application note and PCIe Clock Jitter Tool measurements.

How is the SI5338H-B-GMR programmed, and is external non-volatile memory required?

The SI5338H-B-GMR is programmed via its I²C/SMBus interface using ClockBuilder Pro software. Configuration is stored in on-chip one-time-programmable (OTP) memory, eliminating the need for external EEPROM or flash. Factory-programmed devices power up with valid clocks in <2 ms; field updates can be performed dynamically via I²C without reset.

Can the SI5338H-B-GMR generate different output voltages on each channel?

Yes - the SI5338H-B-GMR provides four independent VDDOx pins (VDDO0–VDDO3), allowing each output driver to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components (e.g., 1.8 V FPGA I/O banks and 3.3 V legacy peripherals) without external level shifters or discrete regulators.

What crystal frequency ranges does the SI5338H-B-GMR support, and what load capacitance is required?

The SI5338H-B-GMR supports external crystals from 8 to 30 MHz in four bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. On-chip load capacitance is configurable for 11–13 pF (supported) with 17–19 pF recommended; crystal ESR must be ≤300 Ω (8–11 MHz) down to ≤75 Ω (26–30 MHz), and drive level must not exceed 100 µW.

SI5338H-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338H-B-GMR FAQ

1.How can I place an order for SI5338H-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338H-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338H-B-GMR reliable?

The price and inventory of SI5338H-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338H-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5338H-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338H-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338H-B-GMR?

SI5338H-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338H-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338H-B-GMR?

For technical support, including SI5338H-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338H-B-GMR requirements.

6.How does Aetrix verify that SI5338H-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338H-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338H-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5338H-B-GMR?

All SI5338H-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338H-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338H-B-GMR part is unused and in its original packaging.

Return procedure for SI5338H-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…