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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338J-B04769-GM

Name: SI5338J-B04769-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338J-B04769-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338J-B04769-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338J-B04769-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338J-B04769-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and 10 GbE line cards.

For engineers reviewing the SI5338J-B04769-GM datasheet, SI5338J-B04769-GM pinout, SI5338J-B04769-GM application, or SI5338J-B04769-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus programming interface.

Technical Context

The SI5338J-B04769-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable drive strength and common-mode voltage.

It features real-time frequency and phase adjustment via dedicated pins (FINC/FDEC, PINC/PDEC) with 1 ppm step resolution and <20 ps phase step accuracy, plus loss-of-lock and loss-of-signal alarms. External feedback mode enables zero-delay operation, and internal OTP memory stores factory-programmed configurations.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 Common Clock specs
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Voltage Per Driver	Independently selectable: 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enables mixed-voltage system clocking
Core Supply	Single 1.8 V / 2.5 V / 3.3 V supply; 45 mA typical current at 100 MHz on all outputs
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for dense PCB layouts
Operating Temperature	–40 °C to +85 °C ambient - qualified for industrial and telecom infrastructure use

Pinout & Package

SI5338J-B04769-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with configurable VDDOx (1.5–3.3 V)
VDDO0–VDDO3	Output buffer supplies	Independent power rails per output bank - enable mixed-signal voltage domain interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise clock generation
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz bus; supports configuration and status readback during operation
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock and loss-of-signal events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
Any-frequency synthesis per output	Four independent MultiSynth™ engines deliver true zero-ppm accuracy across 0.16–710 MHz without external VCXOs
PCIe Gen 1–4 timing compliance	Meets PCIe Gen 3 SRNS (0.11–0.32 ps RMS) and Gen 4 Common Clock (0.15–0.45 ps RMS) jitter requirements out-of-box
Glitchless frequency tuning	Pin-controlled FINC/FDEC inputs enable real-time 1 ppm-step frequency adjustments without output interruption
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in noise-sensitive systems
Flexible reference input	Supports six reference types (crystal, CMOS, SSTL, HSTL, LVDS, LVPECL) - simplifies migration from legacy clock trees
Factory-programmed OTP	Pre-configured startup behavior stored in one-time-programmable memory - eliminates boot-time I²C initialization

Applications

PCIe Switch Timing	Ethernet Line Card
Use Scenario: High-density 16-lane PCIe Gen 4 switch ASIC requiring four synchronized clocks (100 MHz ref, 125 MHz SerDes, 156.25 MHz PHY, 312.5 MHz CDR). IC Role / Device Role / Timing Role: Quad clock generator providing independent, jitter-compliant frequencies with shared low-noise VCO and deterministic skew control. Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk.	Use Scenario: 10 GbE line card with MAC, PHY, and packet processor needing 156.25 MHz, 312.5 MHz, 125 MHz, and 250 MHz clocks. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering precise Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board area vs. multiple XO solutions; supports IEEE 802.3bj jitter specs via <0.7 ps RMS phase jitter.
Broadcast Video Sync	FPGA-Based Compute Accelerator
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring 74.25 MHz, 148.5 MHz, 297 MHz, and 594 MHz pixel clocks with sub-20 ps inter-output skew. IC Role / Device Role / Timing Role: Low-jitter quad clock source with independent phase alignment per output for multi-channel video sampling. Use Value: Enables deterministic inter-channel timing alignment (<100 ps skew) and eliminates frame sync errors in 4K/8K broadcast gear.	Use Scenario: AI inference accelerator using Xilinx Versal FPGA with DDR4 memory, PCIe Gen 5 host interface, and 100G Ethernet MAC. IC Role / Device Role / Timing Role: Configurable clock hub generating DDR4 PHY clock (1200 MHz DDR), PCIe reference (100 MHz), and Ethernet TX/RX clocks (322.265625 MHz). Use Value: Supports heterogeneous clock domains from one device; avoids external jitter cleaners and reduces power vs. discrete PLL+buffer solutions.

PCIe Switch Timing

Ethernet Line Card

Use Scenario: High-density 16-lane PCIe Gen 4 switch ASIC requiring four synchronized clocks (100 MHz ref, 125 MHz SerDes, 156.25 MHz PHY, 312.5 MHz CDR).

IC Role / Device Role / Timing Role: Quad clock generator providing independent, jitter-compliant frequencies with shared low-noise VCO and deterministic skew control.

Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk.

Use Scenario: 10 GbE line card with MAC, PHY, and packet processor needing 156.25 MHz, 312.5 MHz, 125 MHz, and 250 MHz clocks.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering precise Ethernet-compliant frequencies from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and board area vs. multiple XO solutions; supports IEEE 802.3bj jitter specs via <0.7 ps RMS phase jitter.

Broadcast Video Sync

FPGA-Based Compute Accelerator

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring 74.25 MHz, 148.5 MHz, 297 MHz, and 594 MHz pixel clocks with sub-20 ps inter-output skew.

IC Role / Device Role / Timing Role: Low-jitter quad clock source with independent phase alignment per output for multi-channel video sampling.

Use Value: Enables deterministic inter-channel timing alignment (<100 ps skew) and eliminates frame sync errors in 4K/8K broadcast gear.

Use Scenario: AI inference accelerator using Xilinx Versal FPGA with DDR4 memory, PCIe Gen 5 host interface, and 100G Ethernet MAC.

IC Role / Device Role / Timing Role: Configurable clock hub generating DDR4 PHY clock (1200 MHz DDR), PCIe reference (100 MHz), and Ethernet TX/RX clocks (322.265625 MHz).

Use Value: Supports heterogeneous clock domains from one device; avoids external jitter cleaners and reduces power vs. discrete PLL+buffer solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports PCIe Gen 5	Targets next-gen switches and AI accelerators requiring >4 clocks or tighter jitter budgets	Select when upgrading beyond Gen 4 PCIe or needing >4 outputs; requires updated ClockBuilder Pro config
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only	Cost-sensitive, static-clock applications like legacy storage controllers or fixed-rate video encoders	Choose for simple drop-in replacement where frequency flexibility and low jitter are secondary to unit cost

Compared with SI5338J-B04769-GM, Si5332A-D06889-GM offers superior jitter and scalability but increases design complexity and cost, while ICS8430I-01T sacrifices programmability and jitter performance for simplicity and price - making SI5338J-B04769-GM the optimal balance for Gen 4 PCIe and multi-standard timing in industrial and telecom platforms.

Availability

SI5338J-B04769-GM is available at Aetrix Electronics and suitable for PCIe switch timing, 10 GbE line cards, broadcast video synchronization, and FPGA-based compute accelerators requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338J-B04769-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock IC expertise.

The Si5338 family was designed for high-performance, multi-protocol clock generation in data center, telecom, and broadcast equipment - enabling consolidation of discrete oscillators into a single programmable, low-jitter timing IC.

FAQ

What is the default startup configuration of the SI5338J-B04769-GM?

The SI5338J-B04769-GM ships with factory-programmed OTP memory containing a pre-defined configuration. Upon power-up, it begins generating clocks within 2 ms without requiring I²C initialization - ideal for systems with strict boot-time constraints. This default state can be overwritten via I²C if custom timing is needed.

Does the SI5338J-B04769-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338J-B04769-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks AN562 guidelines. Its 0.7 ps RMS typical phase jitter and optimized PLL loop bandwidth (1.6–4 MHz) ensure conformance without external jitter cleaning.

Can the SI5338J-B04769-GM generate frequencies above 350 MHz on all four outputs simultaneously?

No. The SI5338J-B04769-GM supports only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. Outputs above 350 MHz must share these two synthesis paths; other outputs are limited to ≤350 MHz.

How does the SI5338J-B04769-GM handle loss-of-signal detection?

The SI5338J-B04769-GM monitors all six input pins (IN1–IN6) for loss-of-signal (LOS) with 2.6–5 µs detection time and 0.01–1 µs release time. Detected events trigger the open-drain INTR pin and are readable via I²C register 0x000D, enabling fail-safe system response in telecom and industrial applications.

Is ClockBuilder Pro software required to configure the SI5338J-B04769-GM?

ClockBuilder Pro is strongly recommended but not mandatory: it provides GUI-based configuration, jitter simulation, and .hex file generation for OTP programming. However, the SI5338J-B04769-GM can also be configured in-system via standard I²C writes to its 256-byte register map - enabling runtime reprogramming in field-upgradable systems.

SI5338J-B04769-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338J-B04769-GM FAQ

1.How can I place an order for SI5338J-B04769-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338J-B04769-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338J-B04769-GM reliable?

The price and inventory of SI5338J-B04769-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338J-B04769-GM is usually 5 days.

3.What payment methods are accepted for SI5338J-B04769-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338J-B04769-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338J-B04769-GM?

SI5338J-B04769-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338J-B04769-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338J-B04769-GM?

For technical support, including SI5338J-B04769-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338J-B04769-GM requirements.

6.How does Aetrix verify that SI5338J-B04769-GM is sourced from the original manufacturer or authorized distributors?

All SI5338J-B04769-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338J-B04769-GM meets industry standards.

7.What is the process for return or replacement of SI5338J-B04769-GM?

All SI5338J-B04769-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338J-B04769-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338J-B04769-GM part is unused and in its original packaging.

Return procedure for SI5338J-B04769-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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