Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338J-B-GMR

Name: SI5338J-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338J-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338J-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338J-B-GMR.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,866

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338J-B-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338J-B-GMR datasheet, SI5338J-B-GMR pinout, SI5338J-B-GMR application, or SI5338J-B-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), flexible reference inputs (crystal, CMOS, SSTL/HSTL, differential), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338J-B-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by a fractional-N MultiSynth™ synthesis stage per output, enabling independent frequency, phase, and spread-spectrum control. Its core operates from a single 1.8/2.5/3.3 V supply with 45 mA typical current draw.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supplies, programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - covers PCIe, Ethernet, Fibre Channel, and processor clocking needs
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interface to FPGAs, ASICs, and SerDes without level-shifting
Supply Voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V - supports mixed-voltage system designs
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts

Pinout & Package

SI5338J-B-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are defined per Skyworks Rev. 1.6 datasheet (page 37), with dedicated differential input pairs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), three independent VDDO supplies, shared VDD and GND, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS-level signals; tolerate up to 3.73 V input voltage
CLK0A/B–CLK3A/B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with format- and frequency-specific voltage swing
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank - enable mixed-signal interface without external level shifters
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface for configuration and status readback
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables true zero-ppm frequency accuracy on all four outputs with independent integer/fractional-N dividers
Independent phase adjustment	±45 ns range in <20 ps steps - supports precise skew alignment across multi-lane SerDes interfaces
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement - enables dynamic clock rate adaptation without output interruption
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz modulation - reduces EMI in noise-sensitive systems
External feedback mode	Supports zero-delay clock distribution - eliminates propagation delay between input and output clocks

Applications

PCIe Gen 3/4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized reference clocks to multiple PCIe root complexes and endpoints in server backplanes. IC Role / Device Role / Timing Role: Quad-output common clock source meeting PCIe Gen 3 SRNS and Gen 4 jitter specs (0.11–0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and switch fabric ASICs. IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering low-jitter clocks directly to Ethernet MAC/PHY devices. Use Value: Supports mixed-rate Ethernet timing from a single device with independent voltage and format per port.
FPGA/ASIC Clock Distribution	Broadcast Video Timing
Use Scenario: Supplying multiple clock domains (e.g., 100 MHz system, 200 MHz DDR, 400 MHz transceiver) to Xilinx or Intel FPGAs. IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO supplies and phase alignment. Use Value: Enables clean, skew-controlled clocking to heterogeneous FPGA I/O banks without external buffers or level shifters.	Use Scenario: Generating SMPTE-compliant 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks for 4K/8K video encoders and transport systems. IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer supporting exact broadcast frequencies with zero ppm error. Use Value: Meets stringent jitter requirements (<1 ps RMS) for uncompressed video timing without crystal multiplication artifacts.

PCIe Gen 3/4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized reference clocks to multiple PCIe root complexes and endpoints in server backplanes.

IC Role / Device Role / Timing Role: Quad-output common clock source meeting PCIe Gen 3 SRNS and Gen 4 jitter specs (0.11–0.45 ps RMS).

Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and switch fabric ASICs.

IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering low-jitter clocks directly to Ethernet MAC/PHY devices.

Use Value: Supports mixed-rate Ethernet timing from a single device with independent voltage and format per port.

FPGA/ASIC Clock Distribution

Broadcast Video Timing

Use Scenario: Supplying multiple clock domains (e.g., 100 MHz system, 200 MHz DDR, 400 MHz transceiver) to Xilinx or Intel FPGAs.

IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO supplies and phase alignment.

Use Value: Enables clean, skew-controlled clocking to heterogeneous FPGA I/O banks without external buffers or level shifters.

Use Scenario: Generating SMPTE-compliant 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks for 4K/8K video encoders and transport systems.

IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer supporting exact broadcast frequencies with zero ppm error.

Use Value: Meets stringent jitter requirements (<1 ps RMS) for uncompressed video timing without crystal multiplication artifacts.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GMR	Same silicon, factory-programmed with default register map; lacks OTP NVM customization capability	Pre-configured for common use cases; not field-reprogrammable via I²C	Select when fixed configuration suffices and field tuning is unnecessary
LMK04832ISQE/NOPB	Two-stage jitter cleaner with dual-loop architecture; higher power (120 mA), larger 48-QFN package	Optimized for ultra-low additive jitter cleaning rather than multi-frequency synthesis	Select when input clock cleanup is primary requirement, not flexible frequency generation

Compared with Si5338A-B-GMR, SI5338J-B-GMR offers field-programmable OTP memory for custom configurations; compared with LMK04832ISQE/NOPB, it delivers lower power, smaller footprint, and broader frequency flexibility at the expense of jitter cleaning depth.

Availability

SI5338J-B-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabrics, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and consistent electrical performance across production batches.

Supply support for SI5338J-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed for high-performance, software-defined clock generation in datacenter, networking, and multimedia systems where multi-frequency, low-jitter, and programmable timing are critical.

FAQ

What is the maximum output frequency supported by SI5338J-B-GMR in LVPECL format?

The SI5338J-B-GMR supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks datasheet. This capability enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10 GbE applications without frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper layout and termination per Skyworks AN562 guidelines.

Does SI5338J-B-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338J-B-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' recommended settings and layout. The device achieves this using its optimized PLL loop bandwidth (2–5 MHz) and low-noise MultiSynth™ synthesis, and is validated using the Skyworks PCIe Clock Jitter Tool per AN562.

Can SI5338J-B-GMR generate different output voltages on each channel?

Yes, SI5338J-B-GMR provides independent VDDO0–VDDO3 supplies, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage FPGAs, ASICs, and PHYs without external level translators - for example, driving 1.8 V LVDS SerDes and 3.3 V CMOS logic from the same device.

How is SI5338J-B-GMR programmed in-system?

SI5338J-B-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration is stored in one-time-programmable (OTP) non-volatile memory, enabling boot-up without host intervention. Field updates are supported, and register maps can be generated and verified before programming.

What is the thermal performance of SI5338J-B-GMR in continuous operation?

SI5338J-B-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. With typical core current of 45 mA at 3.3 V (148.5 mW dissipation), junction temperature rise is ~5.5 °C above ambient - well within its 150 °C absolute maximum rating. For sustained high-frequency operation, use of the exposed thermal pad per JEDEC MO-220 guidelines is required.

SI5338J-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338J-B-GMR FAQ

1.How can I place an order for SI5338J-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338J-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338J-B-GMR reliable?

The price and inventory of SI5338J-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338J-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5338J-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338J-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338J-B-GMR?

SI5338J-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338J-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338J-B-GMR?

For technical support, including SI5338J-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338J-B-GMR requirements.

6.How does Aetrix verify that SI5338J-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338J-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338J-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5338J-B-GMR?

All SI5338J-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338J-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338J-B-GMR part is unused and in its original packaging.

Return procedure for SI5338J-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…