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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B04065-GMR

Name: SI5338K-B04065-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B04065-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338K-B04065-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338K-B04065-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338K-B04065-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338K-B04065-GMR datasheet, SI5338K-B04065-GMR pinout, SI5338K-B04065-GMR application, or SI5338K-B04065-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338K-B04065-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports true zero-ppm frequency accuracy and <20 ps phase step resolution.

Its output stage provides flexible signal formatting-LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL-with independent VDDO per driver and programmable slew rate, drive strength, and termination. The device supports glitchless frequency increment/decrement (1 ppm steps) and external feedback for zero-delay mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently selectable
Supply Voltages	VDD core: 1.8/2.5/3.3 V; VDDO per output: 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338K-B04065-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad (GND-connected). Pin 1 is top-left corner (IN1), with pins numbered counterclockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent output channels; each pair configurable as LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, logic, and MultiSynth engines
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation on all four outputs with true zero-ppm accuracy and 1 ppb resolution
PCIe Gen 1–4 compliance	Meets PCIe Gen 3 SRNS and Gen 4 common clock jitter specs (≤0.45 ps RMS) without external filtering
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI
Glitchless frequency tuning	Hardware-supported 1 ppm increment/decrement via PINC/FDEC pins; no output interruption during adjustment
Phase alignment control	Independent ±45 ns initial phase offset and <20 ps step resolution per output for skew management

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned PCIe-compliant clocks with independent SSC control per port. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures Gen 4 link stability via ≤0.45 ps RMS jitter.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Enables single-reference design across multi-rate ports; avoids external dividers/multipliers and maintains <10 ps pk-pk period jitter.
Broadcast Video Sync	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks to SDI transceivers and frame synchronizers. IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution for genlock and lip-sync alignment across video pipelines. Use Value: Achieves <±1 ns inter-channel skew across three outputs; supports dynamic format switching without PLL relock delay.	Use Scenario: Supplying 500 MHz system clock, 250 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP and associated memory subsystems. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA timing domains with independent voltage and format per rail. Use Value: Enables 1.8 V I/O domain clocking (LVDS), 1.2 V core clocking (HCSL), and 3.3 V peripheral clocking (CMOS) from one IC.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned PCIe-compliant clocks with independent SSC control per port.

Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures Gen 4 link stability via ≤0.45 ps RMS jitter.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular Ethernet switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Enables single-reference design across multi-rate ports; avoids external dividers/multipliers and maintains <10 ps pk-pk period jitter.

Broadcast Video Sync

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks to SDI transceivers and frame synchronizers.

IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution for genlock and lip-sync alignment across video pipelines.

Use Value: Achieves <±1 ns inter-channel skew across three outputs; supports dynamic format switching without PLL relock delay.

Use Scenario: Supplying 500 MHz system clock, 250 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP and associated memory subsystems.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal FPGA timing domains with independent voltage and format per rail.

Use Value: Enables 1.8 V I/O domain clocking (LVDS), 1.2 V core clocking (HCSL), and 3.3 V peripheral clocking (CMOS) from one IC.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06181-GM	Higher integration: includes integrated crystal; lower jitter (0.35 ps RMS); supports up to 12 outputs via fanout	Targeted at space-constrained systems requiring ultra-low jitter and reduced BOM count; lacks independent VDDO per output	Preferred when crystal integration and sub-0.4 ps jitter are mandatory; not drop-in due to different pinout and register map
ICS853S02IAGLF	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; 3.3 V only; no spread spectrum	Used in cost-sensitive, static-clocking applications where frequency flexibility is unnecessary	Select only for legacy designs with fixed 100/125 MHz requirements; requires redesign for any frequency change

Compared with Si5332A-D06181-GM and ICS853S02IAGLF, SI5338K-B04065-GMR offers unique balance of field-programmability, independent output voltage control, and PCIe Gen 4 compliance in a compact 24-QFN - making it optimal for new designs requiring adaptability across high-speed serial protocols without sacrificing jitter performance.

Availability

SI5338K-B04065-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video sync, and FPGA processor clocking requiring stable component supply and long-term industrial availability.

Supply support for SI5338K-B04065-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed as a programmable, low-jitter quad clock generator targeting high-speed serial interface timing in datacenter, telecom, and broadcast infrastructure - emphasizing flexibility, precision, and compliance with PCIe, Ethernet, and SMPTE standards.

FAQ

What is the maximum output frequency supported by SI5338K-B04065-GMR?

The SI5338K-B04065-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined in the synthesis architecture. All outputs maintain ≤0.7 ps RMS jitter within their respective rated ranges.

Does SI5338K-B04065-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338K-B04065-GMR is explicitly validated for PCIe Gen 4 Common Clock compliance with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks' recommended settings (PLL bandwidth 2–5 MHz, CDR = 10 MHz). This is confirmed in Table 12 of the Rev. 1.6 datasheet and supported by the Skyworks PCIe Clock Jitter Tool.

Can SI5338K-B04065-GMR generate different output voltages on each channel?

Yes, SI5338K-B04065-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O, 2.5 V PHY, 3.3 V controller) without level shifters - a capability confirmed in the "Independent output voltage per driver" feature list and Table 3 DC characteristics.

How is SI5338K-B04065-GMR programmed, and what software is required?

SI5338K-B04065-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software - a free, GUI-based tool that auto-generates configuration files, validates timing constraints, and supports in-system programming. The device's OTP NVM stores the final configuration, enabling autonomous startup without host intervention after initial programming.

What is the thermal performance of SI5338K-B04065-GMR in continuous operation?

SI5338K-B04065-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions and junction-to-case (θJC) of 10 °C/W. With typical core current of 45 mA at 3.3 V and output currents up to 30 mA per channel, power dissipation remains below 250 mW - ensuring reliable operation within the full –40 to +85 °C range when mounted on a standard 2-layer PCB with adequate copper pour under the exposed pad.

SI5338K-B04065-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338K-B04065-GMR FAQ

1.How can I place an order for SI5338K-B04065-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B04065-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B04065-GMR reliable?

The price and inventory of SI5338K-B04065-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B04065-GMR is usually 5 days.

3.What payment methods are accepted for SI5338K-B04065-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B04065-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B04065-GMR?

SI5338K-B04065-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B04065-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B04065-GMR?

For technical support, including SI5338K-B04065-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B04065-GMR requirements.

6.How does Aetrix verify that SI5338K-B04065-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338K-B04065-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B04065-GMR meets industry standards.

7.What is the process for return or replacement of SI5338K-B04065-GMR?

All SI5338K-B04065-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B04065-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B04065-GMR part is unused and in its original packaging.

Return procedure for SI5338K-B04065-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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