Skyworks Solutions Inc. SI5338K-B04912-GM
- Part No.:
- SI5338K-B04912-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338K-B04912-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338K-B04912-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and broadcast video timing systems.
For engineers reviewing the SI5338K-B04912-GM datasheet, SI5338K-B04912-GM pinout, SI5338K-B04912-GM application, or SI5338K-B04912-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).
Technical Context
The SI5338K-B04912-GM implements a two-stage PLL architecture with a high-frequency VCO and patented MultiSynth™ fractional-N synthesis per output channel, enabling independent frequency, phase, and spread-spectrum control. Each of the four output drivers supports integer or fractional mode operation with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement in 1 ppm steps.
Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. The device uses a single core supply (1.8/2.5/3.3 V) with excellent PSRR and supports loss-of-lock and loss-of-signal alarms via dedicated INTR pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements for high-speed serial links. |
| Output Frequency Range | 0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz). |
| Input Reference Options | Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system clock sourcing without external buffers. |
| Output Voltage per Driver | 1.5/1.8/2.5/3.3 V - allows direct interface to mixed-voltage SoCs, FPGAs, and SerDes without level-shifting components. |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts and automated assembly. |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments with no derating required. |
| Core Supply Current | 45 mA typ at 100 MHz on all outputs - low power consumption enables use in thermally constrained embedded systems. |
Pinout & Package
SI5338K-B04912-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A/CLK0B | Differential Output Pair 0 | LVPECL/LVDS/HCSL/CML-capable; independently configurable frequency, format, and voltage (VDDO0). |
| CLK1A/CLK1B | Differential Output Pair 1 | Same capabilities as CLK0; supports integer/fractional synthesis and ±45 ns phase adjustment. |
| CLK2A/CLK2B | Differential Output Pair 2 | Configurable independently; supports spread spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). |
| CLK3A/CLK3B | Differential Output Pair 3 | Final output pair; supports external feedback for zero-delay mode and loss-of-signal detection. |
| IN1/IN2, IN5/IN6 | Differential Input Pairs | Accept 5–710 MHz differential clocks; internal 10 kΩ termination and 3.5 pF capacitance. |
| IN3/IN4 | Single-Ended Input Pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD. |
| SCL/SDA | I²C Interface | SMBus-compatible 2-wire serial bus (up to 400 kHz); used for configuration and status readback. |
| INTR | Interrupt Output | Open-drain alarm signal indicating loss-of-lock or loss-of-signal events. |
| VDD, VDDO0–VDDO3 | Power Supplies | Separate core (VDD) and per-output buffer (VDDOx) supplies enable mixed-voltage operation. |
| GND, RSVD_GND | Ground Terminals | Multiple GND pins and reserved ground pad ensure low-impedance return paths and thermal dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Any-Frequency Synthesis | Four outputs each generate arbitrary frequencies from 0.16 to 710 MHz with true zero-ppm accuracy using MultiSynth™ technology. |
| PCIe Gen 4 Compliance | 0.15–0.45 ps RMS jitter in Common Clock mode meets PCI Express Base Specification 4.0 rev. 0.5 requirements. |
| Per-Output Voltage Control | VDDO0–VDDO3 support 1.5/1.8/2.5/3.3 V independently - eliminates external level shifters for multi-rail systems. |
| Glitchless Frequency Adjustment | Frequency increment/decrement in 1 ppm steps with update time ≤667 ns (pin-controlled) enables dynamic clock scaling without disruption. |
| Programmable Spread Spectrum | Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI in noise-sensitive applications. |
| External Feedback Mode | Supports zero-delay operation by feeding CLKOUT back to reference input - critical for deterministic latency in timing-critical systems. |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 1–4 Clocking |
|---|---|
Use Scenario: Synchronizing packet forwarding engines, PHYs, and management controllers in Layer 3 switches with multiple line rates (1G/10G/25G). IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, 312.5 MHz, and 625 MHz clocks with sub-ps jitter. Use Value: Enables simultaneous support of IEEE 802.3ae, 802.3ba, and 802.3by standards while meeting SONET OC-12 (0.7 ps RMS) and PCIe Gen 4 jitter limits. | Use Scenario: Delivering compliant reference clocks to CPU, GPU, NVMe SSDs, and add-in cards in servers and workstations. IC Role / Device Role / Timing Role: PCIe Common Clock source with SRNS support for Gen 3 and jitter-filtered Gen 4 operation. Use Value: Meets Intel Clock Jitter Tool v1.6.4 validation for total jitter ≤33.6 ps pk-pk (Gen 2) and RMS jitter ≤0.45 ps (Gen 4), eliminating need for discrete jitter cleaners. |
| Broadcast Video/Audio Timing | FPGA & Processor Clocking |
Use Scenario: Generating SMPTE ST 2082 (12G-SDI), AES67, and Dolby Atmos reference clocks in production switchers and audio interfaces. IC Role / Device Role / Timing Role: Low-jitter any-frequency synthesizer delivering 74.25 MHz, 148.5 MHz, 297 MHz, and 594 MHz with <20 ps phase step resolution. Use Value: Supports frame-accurate genlock across multiple video pipelines and eliminates timing skew between audio/video subsystems. | Use Scenario: Providing configurable clocks to Xilinx Versal, Intel Agilex, and Arm-based SoCs requiring multiple domain-specific frequencies (e.g., DDR, AXI, PCIe, USB). IC Role / Device Role / Timing Role: Programmable clock source with independent voltage per output driving mixed-voltage I/O banks. Use Value: Reduces BOM count by replacing discrete oscillators and buffers; simplifies layout with single 4×4 mm QFN instead of four 2.5×2.0 mm crystals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06912-GM | Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 5×5 mm 32-QFN package. | Targeted at next-gen data center switches requiring ultra-low jitter and >4 outputs; not drop-in compatible due to pin count and footprint change. | Select when PCIe Gen 5 readiness, integrated crystal, or >4 outputs are required; SI5338K-B04912-GM remains optimal for cost-sensitive, space-constrained Gen 4 designs. |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming), 1.2 ps RMS jitter, 3.3 V only, 32-TQFP package. | Used in legacy telecom line cards where frequency flexibility is unnecessary and board area is less constrained. | Choose only for fixed-frequency applications with no requirement for reconfiguration; SI5338K-B04912-GM provides field-upgradable timing and superior jitter performance. |
Compared with Si5332A-D06912-GM and ICS8430I-01T, SI5338K-B04912-GM uniquely balances programmability, PCIe Gen 4 compliance, compact 4×4 mm footprint, and industrial temperature range - making it the preferred choice for mid-generation upgrades and mixed-signal FPGA platforms.
Availability
SI5338K-B04912-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clocking, and broadcast video/audio timing requiring stable component supply and long-term industrial availability.
Supply support for SI5338K-B04912-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing expertise.
The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in networking, computing, and broadcast equipment - emphasizing low jitter, I²C configurability, and mixed-signal interface flexibility.
FAQ
What is the maximum output frequency supported by SI5338K-B04912-GM in LVPECL mode?
The SI5338K-B04912-GM supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability applies when operating in integer synthesis mode with appropriate VCO and MultiSynth divider settings, and is validated for jitter performance per PCIe Gen 4 specifications.
Does SI5338K-B04912-GM support spread spectrum clocking (SSC) on all four outputs?
Yes, SI5338K-B04912-GM supports independent spread spectrum modulation on any output, with programmable spread depth (0.5–5.0%), modulation rate (33–63 kHz), and center frequency (5–350 MHz). This feature is implemented per-output and does not require shared resources, enabling simultaneous SSC on multiple clocks without interference.
Can SI5338K-B04912-GM operate with a 25 MHz crystal input?
No - SI5338K-B04912-GM supports external crystals only in the 8–30 MHz range, and 25 MHz falls within that range. The device's on-chip crystal oscillator circuit is qualified for 25 MHz operation per Tables 8–11, with recommended load capacitance of 17–19 pF and max drive level of 100 µW.
What is the purpose of the INTR pin on SI5338K-B04912-GM?
The INTR pin on SI5338K-B04912-GM is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) conditions. It is electrically compatible with 1.8/2.5/3.3 V logic systems and supports pull-up resistor configurations per Table 7, enabling real-time fault monitoring without host processor polling.
How does SI5338K-B04912-GM achieve zero-ppm frequency accuracy?
SI5338K-B04912-GM achieves true zero-ppm frequency accuracy through its MultiSynth™ fractional-N synthesis architecture, which calculates exact integer or fractional divider ratios to generate target frequencies without rounding error. This is verified across all four outputs simultaneously, as stated in the device description and confirmed in Table 5 (frequency synthesis resolution: 1 ppb).
SI5338K-B04912-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338K-B04912-GM FAQ
1.How can I place an order for SI5338K-B04912-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338K-B04912-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338K-B04912-GM reliable?
The price and inventory of SI5338K-B04912-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B04912-GM is usually 5 days.
3.What payment methods are accepted for SI5338K-B04912-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B04912-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338K-B04912-GM?
SI5338K-B04912-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338K-B04912-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338K-B04912-GM?
For technical support, including SI5338K-B04912-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B04912-GM requirements.
6.How does Aetrix verify that SI5338K-B04912-GM is sourced from the original manufacturer or authorized distributors?
All SI5338K-B04912-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B04912-GM meets industry standards.
7.What is the process for return or replacement of SI5338K-B04912-GM?
All SI5338K-B04912-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B04912-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338K-B04912-GM part is unused and in its original packaging.
Return procedure for SI5338K-B04912-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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