Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B05046-GM

Name: SI5338K-B05046-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B05046-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338K-B05046-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338K-B05046-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,778

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338K-B05046-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for input frequencies up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switches.

For engineers reviewing the SI5338K-B05046-GM datasheet, SI5338K-B05046-GM pinout, SI5338K-B05046-GM application, or SI5338K-B05046-GM equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement capability, and 24-pin 4×4 mm QFN package with validated thermal resistance (θ_JA = 37 °C/W).

Technical Context

The SI5338K-B05046-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ synthesis blocks, each capable of integer or fractional-N frequency generation. Its programmable loop bandwidth (1.6 MHz typical) and external feedback mode enable zero-delay operation and precise jitter filtering.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage selection (VDDO0–VDDO3), programmable initial phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Count & Type	4 differential outputs (CLK0A/B–CLK3A/B) or up to 8 single-ended; supports mixed-mode configuration
Frequency Range	0.16–710 MHz per output; 2 unique frequencies >350 MHz simultaneously (Fvco/4, Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Core Supply	1.8 V / 2.5 V / 3.3 V ±10%; 45 mA typical current at 100 MHz on all outputs
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; θ_JA = 37 °C/W, θ_JC = 10 °C/W
Operating Temp	–40 °C to +85 °C ambient; qualified per industrial temperature grade

Pinout & Package

SI5338K-B05046-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across Si5338 family variants and validated per Skyworks Rev. 1.6 datasheet (page 33).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V per output group; enables mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise clock generation
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz control bus; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal alarms

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode; validated per PCI Express Base Spec 4.0 rev. 0.5
Glitchless frequency tuning	1 ppm step size via PINC/FDEC pins; update time <667 ns for outputs >18 MHz
Programmable phase offset	±45 ns range in <20 ps steps; enables skew compensation across multi-lane interfaces
Spread-spectrum control	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI in dense PCB layouts
Zero-delay mode	External feedback path allows synchronous clock forwarding without added latency

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched phase alignment. Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) while eliminating discrete oscillator count and board space.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in Layer-3 switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing three separate crystals; supports IEEE 802.3bj/802.3by jitter requirements. Use Value: Enables single-device clock tree with <100 ps output-to-output skew and programmable SSC for EMI reduction.
Broadcast Video Sync	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder ASICs in broadcast cameras. IC Role / Device Role / Timing Role: High-frequency clock generator producing 270 MHz, 540 MHz, and 720 MHz LVDS outputs from a single 27 MHz crystal. Use Value: Achieves <0.7 ps RMS jitter at 720 MHz-critical for minimizing bit error rate in 12G-SDI serial links.	Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP in telecom line cards. IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO rails enabling mixed-voltage FPGA domain interfacing. Use Value: Eliminates need for level translators and discrete buffers; supports dynamic frequency scaling via I²C during runtime.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched phase alignment.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) while eliminating discrete oscillator count and board space.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in Layer-3 switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing three separate crystals; supports IEEE 802.3bj/802.3by jitter requirements.

Use Value: Enables single-device clock tree with <100 ps output-to-output skew and programmable SSC for EMI reduction.

Broadcast Video Sync

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder ASICs in broadcast cameras.

IC Role / Device Role / Timing Role: High-frequency clock generator producing 270 MHz, 540 MHz, and 720 MHz LVDS outputs from a single 27 MHz crystal.

Use Value: Achieves <0.7 ps RMS jitter at 720 MHz-critical for minimizing bit error rate in 12G-SDI serial links.

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 memory clock, and 100 MHz peripheral clock to Xilinx Versal ACAP in telecom line cards.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO rails enabling mixed-voltage FPGA domain interfacing.

Use Value: Eliminates need for level translators and discrete buffers; supports dynamic frequency scaling via I²C during runtime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05089-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external VCXO for best performance	Targeted at ultra-low-jitter 100G/400G optical modules and coherent DSP timing	Select when sub-0.5 ps RMS jitter and >4 outputs are required; higher BOM cost and layout complexity
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Suitable for cost-sensitive, static-clock applications like legacy storage controllers	Choose only if frequency flexibility, phase control, or PCIe Gen 4 compliance are not needed

Compared with Si5332A-D05089-GM and ICS853S01AGI-01LFT, the SI5338K-B05046-GM delivers optimal balance of programmability, PCIe Gen 4 readiness, and thermal efficiency in a compact 4×4 mm footprint-making it ideal for reconfigurable systems where firmware-defined clock trees reduce inventory and accelerate design iteration.

Availability

SI5338K-B05046-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabrics, and broadcast video processing equipment requiring stable component supply and long-term industrial-grade availability.

Supply support for SI5338K-B05046-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock IC expertise.

The Si5338 product line was designed for high-speed serial interface timing in datacenter, telecom, and broadcast systems-emphasizing low jitter, multi-output flexibility, and field-programmability via I²C.

FAQ

What is the maximum output frequency supported by SI5338K-B05046-GM?

The SI5338K-B05046-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet.

Does SI5338K-B05046-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338K-B05046-GM meets PCIe Gen 4 common clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 and tested using the official Skyworks PCIe Clock Jitter Tool. This compliance is explicitly stated in the Features section of the datasheet.

Can SI5338K-B05046-GM operate with a 25 MHz crystal input?

No-SI5338K-B05046-GM supports crystal inputs only in the 8–30 MHz range, and 25 MHz falls within that range. The device's on-chip crystal oscillator circuit is qualified for 25 MHz operation with appropriate load capacitance (17–19 pF recommended), as specified in Tables 8–11 of the datasheet.

What is the thermal resistance (θ_JA) of SI5338K-B05046-GM in its 24-QFN package?

The SI5338K-B05046-GM has a junction-to-ambient thermal resistance (θ_JA) of 37 °C/W under still-air conditions, and junction-to-case (θ_JC) of 10 °C/W, as measured and guaranteed in Table 4 of the Skyworks Rev. 1.6 datasheet. These values are validated for the standard 4×4 mm QFN footprint with exposed thermal pad.

How many independent output voltage supplies does SI5338K-B05046-GM support?

The SI5338K-B05046-GM provides four independent output buffer supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous interfacing with mixed-voltage devices-e.g., 1.8 V FPGA I/O banks and 3.3 V legacy peripherals-without external level shifters.

SI5338K-B05046-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338K-B05046-GM FAQ

1.How can I place an order for SI5338K-B05046-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B05046-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B05046-GM reliable?

The price and inventory of SI5338K-B05046-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B05046-GM is usually 5 days.

3.What payment methods are accepted for SI5338K-B05046-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B05046-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B05046-GM?

SI5338K-B05046-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B05046-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B05046-GM?

For technical support, including SI5338K-B05046-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B05046-GM requirements.

6.How does Aetrix verify that SI5338K-B05046-GM is sourced from the original manufacturer or authorized distributors?

All SI5338K-B05046-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B05046-GM meets industry standards.

7.What is the process for return or replacement of SI5338K-B05046-GM?

All SI5338K-B05046-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B05046-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B05046-GM part is unused and in its original packaging.

Return procedure for SI5338K-B05046-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…