Skyworks Solutions Inc. SI5338K-B05046-GMR

Overview

SI5338K-B05046-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (0.16–710 MHz), supports PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliance, achieves 0.7 ps RMS typical phase jitter, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It is used in high-speed serial interface timing for FPGA-based telecom line cards.

For engineers reviewing the SI5338K-B05046-GMR datasheet, SI5338K-B05046-GMR pinout, SI5338K-B05046-GMR application, or SI5338K-B05046-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% deviation, 33–63 kHz modulation), loss-of-lock/loss-of-signal alarms, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338K-B05046-GMR integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths. Each output driver supports configurable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage (1.5–3.3 V), enabling mixed-signal clock distribution without level-shifting components.

It implements real-time, glitchless frequency adjustment in 1 ppm steps and phase tuning in <20 ps increments per output, with dedicated status pins (INTR) for lock/signal monitoring. External feedback mode enables zero-delay operation, while programmable SSC on any output meets EMI reduction requirements across 5–350 MHz.

Key Specifications

Pinout & Package

SI5338K-B05046-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family: six inputs (IN1–IN6), eight clock outputs (CLK0A/B through CLK3A/B), four VDDOx supplies (VDDO0–VDDO3), dual VDD core supplies, SCL/SDA/I²C interface, INTR alarm, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D05089-GM and ICS8430I-01T, SI5338K-B05046-GMR offers balanced programmability, PCIe Gen 4 compliance, and industrial temperature support in a mature, widely supported 4 × 4 mm QFN - making it optimal for mid-cycle upgrades and mixed-protocol timing in telecom and enterprise infrastructure.

Availability

SI5338K-B05046-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10GbE switch fabrics, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338K-B05046-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-protocol systems - specifically addressing jitter-critical serial interfaces (PCIe, Ethernet, Fibre Channel) and FPGA/ASIC clock trees requiring flexible frequency synthesis and voltage-domain isolation.

FAQ

What is the maximum output frequency supported by SI5338K-B05046-GMR?

The SI5338K-B05046-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the VCO architecture. All outputs maintain 0.7 ps RMS typical jitter within their respective ranges.

Does SI5338K-B05046-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338K-B05046-GMR is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Its measured RMS jitter is ≤0.32 ps (Gen 3 SRNS) and ≤0.45 ps (Gen 4 Common Clock) under specified conditions (PLL BW 2–5 MHz, CDR = 10 MHz), satisfying PCI-SIG Base Specification 4.0 requirements for reference clock performance.

How is SI5338K-B05046-GMR programmed, and what tools are required?

SI5338K-B05046-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. This GUI tool enables full configuration of all outputs (frequency, format, voltage, phase, SSC), saves settings to on-chip OTP NVM, and generates initialization code for embedded systems. No external hardware programmer is needed - only a USB-to-I²C adapter or host microcontroller with I²C capability.

Can SI5338K-B05046-GMR generate different output voltages on each channel?

Yes, SI5338K-B05046-GMR provides four independent VDDOx supplies (VDDO0–VDDO3), allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V - regardless of core VDD. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O banks and 3.3 V legacy PHYs) without external level shifters or discrete regulators.

What is the function of the INTR pin on SI5338K-B05046-GMR?

The INTR pin on SI5338K-B05046-GMR is an active-low, open-drain interrupt output that asserts when either loss-of-lock (LOL) or loss-of-signal (LOS) is detected on any enabled input clock. It allows system-level monitoring without polling registers, enabling rapid fault response in telecom line cards and server platforms where clock integrity is safety-critical.