Skyworks Solutions Inc. SI5338K-B05615-GM
- Part No.:
- SI5338K-B05615-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338K-B05615-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,549
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Product details
Overview
SI5338K-B05615-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338K-B05615-GM datasheet, SI5338K-B05615-GM pinout, SI5338K-B05615-GM application, or SI5338K-B05615-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-QFN package, and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).
Technical Context
The SI5338K-B05615-GM implements a two-stage PLL architecture: a primary synthesis stage (PLL + VCO) generating a high-frequency Fvco, followed by four independent MultiSynth™ fractional-N dividers enabling precise frequency synthesis per output. Each output driver supports configurable format, voltage, and spread-spectrum modulation.
It accepts six input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential - and delivers programmable initial phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and loss-of-lock/loss-of-signal alarms via dedicated INTR pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per channel; supports up to two outputs >350 MHz simultaneously (Fvco/4 & Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Voltage per Driver | Independently configurable: 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enables mixed-voltage system interfacing |
| Core Supply | Single 1.8 V / 2.5 V / 3.3 V supply; 45 mA typical current at 100 MHz on all outputs |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch - space-efficient for dense PCB layouts |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial and telecom line card environments |
Pinout & Package
SI5338K-B05615-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential output pairs | Four independent output channels; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL |
| VDDO0–VDDO3 | Output buffer supply pins | Enable per-channel output voltage selection (1.5/1.8/2.5/3.3 V) |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise timing operation |
| SCL, SDA | I²C interface | SMBus-compatible serial programming interface (up to 400 kHz) |
| INTR | Interrupt output | Open-drain status pin indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs - eliminates need for multiple crystals |
| Independent phase adjustment | ±45 ns range in <20 ps steps per output - supports precise skew management in multi-clock domain systems |
| Spread spectrum modulation | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI without affecting timing integrity |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled increment/decrement - enables real-time dynamic frequency scaling |
| External feedback mode | Supports zero-delay operation - critical for synchronous clock distribution in backplane applications |
Applications
| Ethernet Switch/Routing | PCIe Gen 4 System Clocking |
|---|---|
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across PHY, MAC, and packet processor. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-ps jitter. Use Value: Eliminates four discrete oscillators; maintains PCIe Gen 4 jitter compliance (<0.45 ps RMS) and reduces board area by >60%. |
Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots needing common reference clock and SRNS-compliant timing. IC Role / Device Role / Timing Role: PCIe Common Clock generator delivering 100 MHz HCSL to all slots while supporting SRNS mode for root complex and endpoint synchronization. Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) and enables single-device clock tree simplification versus discrete oscillator + fanout buffer solutions. |
| Broadcast Video Timing | FPGA-Based Signal Processing |
Use Scenario: SMPTE 2110 IP video router requiring genlock-capable 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with tight phase alignment. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE frequencies with programmable phase offsets between outputs. Use Value: Achieves <100 ps output-to-output skew and ±20 ps phase step resolution - essential for frame-accurate video switching. |
Use Scenario: High-throughput radar processing unit using Xilinx Kintex Ultrascale+ FPGA with multiple clock domains (ADC sampling, DSP core, DDR4 memory, PCIe interface). IC Role / Device Role / Timing Role: Configurable clock source delivering 500 MHz (ADC), 300 MHz (DSP), 200 MHz (DDR4), and 250 MHz (PCIe) from one device. Use Value: Enables full-rate ADC sampling and deterministic data path timing while reducing power vs. four separate clock ICs (45 mA vs. >120 mA total). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05615-GM | Higher integration: includes integrated LDOs, enhanced jitter performance (0.35 ps RMS), and wider frequency range (up to 1.2 GHz) | Targeted at next-gen PCIe Gen 5/6 and 400G Ethernet; requires different layout and power design | Select when ultra-low jitter or >710 MHz outputs are required; not drop-in compatible due to different pinout and power architecture |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; no spread spectrum or phase adjustment | Cost-sensitive, static clock trees where frequency flexibility is unnecessary | Choose for simple, low-cost replacement of four fixed-frequency oscillators - lacks SI5338K-B05615-GM's programmability and PCIe Gen 4 compliance |
Compared with Si5332A-D05615-GM and ICS8430I-01T, the SI5338K-B05615-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and industrial temperature operation in a compact 4×4 mm QFN - making it optimal for upgradeable, multi-standard platforms where BOM consolidation and future-proofing matter.
Availability
SI5338K-B05615-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server boards, broadcast video infrastructure, and FPGA-based signal processing systems requiring stable component supply and long-term lifecycle support.
Supply support for SI5338K-B05615-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications infrastructure and high-performance computing.
The Si5338 product line was designed to replace multiple discrete oscillators with a single programmable clock generator for high-speed digital systems - targeting PCIe, Ethernet, and broadcast video applications demanding low jitter and flexible frequency synthesis.
FAQ
What is the maximum output frequency supported by SI5338K-B05615-GM?
The SI5338K-B05615-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - as defined in the synthesis architecture.
Does SI5338K-B05615-GM support PCIe Gen 4 Common Clock and SRNS modes?
Yes, SI5338K-B05615-GM is explicitly compliant with PCIe Gen 4 Common Clock specifications (0.15–0.45 ps RMS jitter) and PCIe Gen 3 SRNS (Separate Reference No Spread) mode (0.11–0.32 ps RMS). Its PLL bandwidth (2–5 MHz) and jitter performance are validated per PCI-SIG requirements.
Can SI5338K-B05615-GM generate different output voltages on each channel?
Yes, SI5338K-B05615-GM provides independent VDDO0–VDDO3 pins, allowing each of its four output drivers to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components such as 1.8 V FPGAs, 3.3 V legacy peripherals, and 2.5 V SerDes blocks without level shifters.
How is SI5338K-B05615-GM programmed, and what tools are required?
SI5338K-B05615-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The tool generates configuration files and supports real-time register editing, jitter simulation, and PCIe compliance validation - eliminating manual register mapping.
What is the thermal performance of SI5338K-B05615-GM in continuous operation?
SI5338K-B05615-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At typical 45 mA core current and 3.3 V supply, power dissipation remains below 150 mW - ensuring reliable operation within the full –40 °C to +85 °C industrial temperature range without forced airflow.
SI5338K-B05615-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338K-B05615-GM FAQ
1.How can I place an order for SI5338K-B05615-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338K-B05615-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338K-B05615-GM reliable?
The price and inventory of SI5338K-B05615-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B05615-GM is usually 5 days.
3.What payment methods are accepted for SI5338K-B05615-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B05615-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338K-B05615-GM?
SI5338K-B05615-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338K-B05615-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338K-B05615-GM?
For technical support, including SI5338K-B05615-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B05615-GM requirements.
6.How does Aetrix verify that SI5338K-B05615-GM is sourced from the original manufacturer or authorized distributors?
All SI5338K-B05615-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B05615-GM meets industry standards.
7.What is the process for return or replacement of SI5338K-B05615-GM?
All SI5338K-B05615-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B05615-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338K-B05615-GM part is unused and in its original packaging.
Return procedure for SI5338K-B05615-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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