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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B05615-GMR

Name: SI5338K-B05615-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B05615-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338K-B05615-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338K-B05615-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338K-B05615-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 4–compliant timing systems.

For engineers reviewing the SI5338K-B05615-GMR datasheet, SI5338K-B05615-GMR pinout, SI5338K-B05615-GMR application, or SI5338K-B05615-GMR equivalent, this device enables precise multi-clock domain synchronization in high-speed serial interfaces, FPGA/processor clocking, and broadcast video timing where zero-ppm accuracy and sub-picosecond jitter are critical.

Technical Context

The SI5338K-B05615-GMR integrates a fractional-N PLL with two-stage MultiSynth synthesis: first stage locks to input references (8–30 MHz crystal or 5–710 MHz differential/CMOS), second stage generates four independent output frequencies with integer or fractional division. Each output path includes programmable voltage (1.5–3.3 V), format selection, and <20 ps phase step resolution.

It features loss-of-lock and loss-of-signal alarms, independent frequency increment/decrement (1 ppm steps), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and external feedback mode for zero-delay operation - all configurable via I²C/SMBus interface with ClockBuilder Pro software support.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B) with optional single-ended configuration
Frequency range per output	0.16–710 MHz (LVPECL/LVDS), 0.16–250 MHz (HCSL), 0.16–350 MHz (SSTL/HSTL), 0.16–200 MHz (CMOS)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 3 SRNS and Gen 4 common clock specs
Supply voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per VDDOx rail
Input reference options	8–30 MHz crystal, or 5–710 MHz differential/CMOS/SSTL/HSTL inputs
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338K-B05615-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), eight output terminals (CLK0A/B–CLK3A/B), four VDDO rails (VDDO0–VDDO3), dual-core VDD, SCL/SDA/I²C interface, INTR alarm, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Configurable LVPECL/LVDS/HCSL/CMOS; supports up to 710 MHz with independent voltage and format
CLK1A / CLK1B	Differential output pair 1	Independent frequency, phase, and format control; synchronized or asynchronous to other outputs
CLK2A / CLK2B	Differential output pair 2	Supports spread-spectrum modulation (0.5–5.0%, 33–63 kHz); usable in PCIe Gen 4 clock trees
CLK3A / CLK3B	Differential output pair 3	Programmable initial phase offset (±45 ns); <20 ps phase step resolution for fine alignment
IN1 / IN2, IN5 / IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled signals; require external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH/VIL thresholds track VDD
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output pair; enable mixed-voltage system interfacing
SCL / SDA	I²C/SMBus interface	Standard 100/400 kHz operation; used for full register configuration and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal on active inputs

Key Features

Feature	Design Value
MultiSynth™ synthesis architecture	Enables true zero-ppm frequency accuracy across all four outputs without trimming or calibration
Independent output voltage per driver	Permits direct interface to mixed-voltage SoCs, FPGAs, and SerDes without level-shifting components
Glitchless frequency adjustment	1 ppm incremental/decremental tuning via dedicated pins or I²C, enabling dynamic clock scaling
Programmable spread spectrum	Reduces EMI in dense PCB layouts by applying user-defined down-spread (0.5–5.0%) at selectable rates
External feedback mode	Supports zero-delay clock distribution by feeding back an output to the reference input path
Loss-of-signal detection	Responds within 2.6–5 µs to input failure, enabling fast failover in redundant timing architectures

Applications

Ethernet Switch Timing	PCIe Gen 4 Root Complex
Use Scenario: 10 GbE switch ASIC requiring synchronous 156.25 MHz and 312.5 MHz clocks with tight skew control across multiple SerDes lanes. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned outputs for MAC, PHY, and packet processor domains. Use Value: Sub-10 ps output-to-output skew and 0.7 ps RMS jitter meet IEEE 802.3bj jitter budgets without external clean-up PLLs.	Use Scenario: Server motherboard with PCIe Gen 4 x16 slot and CPU interconnect needing compliant common clock (100 MHz) plus auxiliary clocks (125 MHz, 250 MHz). IC Role / Device Role / Timing Role: Primary timing IC delivering PCIe Gen 4 common clock and additional reference clocks with SRNS compliance. Use Value: Meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps) and supports simultaneous multi-frequency synthesis from single crystal.
Broadcast Video Synchronization	FPGA-Based Video Processing
Use Scenario: SMPTE ST 2082-1 12G-SDI transmitter requiring genlock-capable 74.25 MHz and 148.5 MHz clocks with frame-accurate phase alignment. IC Role / Device Role / Timing Role: Master clock synthesizer generating genlockable outputs with programmable phase offset and jitter cleaning. Use Value: ±45 ns initial phase offset and <20 ps phase step resolution enable precise frame-synchronous switching between sources.	Use Scenario: High-end video processing FPGA (e.g., Xilinx Versal) needing 300 MHz pixel clock, 150 MHz DDR interface clock, and 200 MHz logic clock from one compact source. IC Role / Device Role / Timing Role: Integrated clock source replacing discrete oscillators and fanout buffers in space-constrained video modules. Use Value: Four independent outputs eliminate board-level clock routing complexity and reduce BOM count by ≥3 components.

Ethernet Switch Timing

PCIe Gen 4 Root Complex

Use Scenario: 10 GbE switch ASIC requiring synchronous 156.25 MHz and 312.5 MHz clocks with tight skew control across multiple SerDes lanes.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned outputs for MAC, PHY, and packet processor domains.

Use Value: Sub-10 ps output-to-output skew and 0.7 ps RMS jitter meet IEEE 802.3bj jitter budgets without external clean-up PLLs.

Use Scenario: Server motherboard with PCIe Gen 4 x16 slot and CPU interconnect needing compliant common clock (100 MHz) plus auxiliary clocks (125 MHz, 250 MHz).

IC Role / Device Role / Timing Role: Primary timing IC delivering PCIe Gen 4 common clock and additional reference clocks with SRNS compliance.

Use Value: Meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps) and supports simultaneous multi-frequency synthesis from single crystal.

Broadcast Video Synchronization

FPGA-Based Video Processing

Use Scenario: SMPTE ST 2082-1 12G-SDI transmitter requiring genlock-capable 74.25 MHz and 148.5 MHz clocks with frame-accurate phase alignment.

IC Role / Device Role / Timing Role: Master clock synthesizer generating genlockable outputs with programmable phase offset and jitter cleaning.

Use Value: ±45 ns initial phase offset and <20 ps phase step resolution enable precise frame-synchronous switching between sources.

Use Scenario: High-end video processing FPGA (e.g., Xilinx Versal) needing 300 MHz pixel clock, 150 MHz DDR interface clock, and 200 MHz logic clock from one compact source.

IC Role / Device Role / Timing Role: Integrated clock source replacing discrete oscillators and fanout buffers in space-constrained video modules.

Use Value: Four independent outputs eliminate board-level clock routing complexity and reduce BOM count by ≥3 components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05615-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and 5G wireless infrastructure with strict deterministic delay requirements	Choose when >4 outputs, ultra-low jitter, or deterministic latency are required; not pin-compatible
ICS8430I-01T	Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz), no I²C programming, higher jitter (1.2 ps RMS)	Limited to fixed-frequency Ethernet/PCIe applications without frequency agility or spread-spectrum capability	Choose for cost-sensitive, non-programmable deployments where flexibility is unnecessary

Compared with SI5338K-B05615-GMR, Si5332A-D05615-GM offers superior jitter and scalability but requires redesign; ICS8430I-01T provides lower cost and simpler integration but lacks programmability and PCIe Gen 4 compliance.

Availability

SI5338K-B05615-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch designs, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338K-B05615-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed for high-performance, multi-clock-domain systems requiring programmable, low-jitter timing - specifically targeting PCIe, Ethernet, broadcast video, and FPGA-based platforms where flexibility and precision outweigh fixed-function simplicity.

FAQ

What is the maximum output frequency supported by SI5338K-B05615-GMR in LVPECL mode?

The SI5338K-B05615-GMR supports up to 710 MHz on LVPECL outputs when configured with appropriate VDDO voltage (2.5 V or 3.3 V) and load conditions. This capability enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10 GbE PHYs without intermediate frequency multiplication.

Does SI5338K-B05615-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338K-B05615-GMR meets PCIe Gen 4 Common Clock RMS jitter specification (≤0.45 ps, 10 kHz–50 MHz) when configured per Skyworks AN562 guidelines using HCSL outputs at 100 MHz and proper layout practices. Its 0.7 ps typical jitter headroom ensures robust margin under real-world noise conditions.

Can SI5338K-B05615-GMR generate four different frequencies simultaneously?

Yes, SI5338K-B05615-GMR uses independent MultiSynth™ synthesis engines per output, allowing four distinct frequencies (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) to be generated concurrently with zero ppm error and sub-20 ps phase step resolution for alignment.

What input reference options does SI5338K-B05615-GMR accept?

SI5338K-B05615-GMR accepts eight input configurations: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential (LVDS/LVPECL/CML). Input selection is fully programmable and supports automatic failover between references.

Is ClockBuilder Pro software required to configure SI5338K-B05615-GMR?

No - SI5338K-B05615-GMR can be configured via standard I²C/SMBus commands using any microcontroller or host processor. ClockBuilder Pro is optional GUI software that simplifies register setup, validates configurations, and exports initialization code; it is not mandatory for basic or custom implementations.

SI5338K-B05615-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338K-B05615-GMR FAQ

1.How can I place an order for SI5338K-B05615-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B05615-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B05615-GMR reliable?

The price and inventory of SI5338K-B05615-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B05615-GMR is usually 5 days.

3.What payment methods are accepted for SI5338K-B05615-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B05615-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B05615-GMR?

SI5338K-B05615-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B05615-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B05615-GMR?

For technical support, including SI5338K-B05615-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B05615-GMR requirements.

6.How does Aetrix verify that SI5338K-B05615-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338K-B05615-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B05615-GMR meets industry standards.

7.What is the process for return or replacement of SI5338K-B05615-GMR?

All SI5338K-B05615-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B05615-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B05615-GMR part is unused and in its original packaging.

Return procedure for SI5338K-B05615-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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