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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B05616-GMR

Name: SI5338K-B05616-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B05616-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338K-B05616-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338K-B05616-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338K-B05616-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS phase jitter, PCIe Gen 1–4 compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs - used in FPGA clocking, Ethernet switches, and PCIe-based server platforms.

For engineers reviewing the SI5338K-B05616-GMR datasheet, SI5338K-B05616-GMR pinout, SI5338K-B05616-GMR application, or SI5338K-B05616-GMR equivalent, this page provides verified specifications, package mapping, functional pin roles, real-world use cases, and validated alternative options for timing-critical embedded and datacom designs.

Technical Context

The SI5338K-B05616-GMR implements a dual-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) followed by four independent MultiSynth™ fractional-N synthesizers per output. Each output supports integer/fractional mode, programmable phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps.

It operates from a single 1.8/2.5/3.3 V core supply and features four independent output buffer supplies (VDDO0–VDDO3), enabling mixed-voltage signaling (1.5–3.3 V). The device supports external crystal (8–30 MHz), CMOS, SSTL/HSTL, and differential inputs - with loss-of-signal and loss-of-lock monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential outputs (CLK0A/B to CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Frequency range	0.16–710 MHz per output; up to two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock specs
Supply voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V
Operating temperature	–40 °C to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management
Control interface	I²C/SMBus-compatible (up to 400 kHz); OTP NVM stores configuration for power-on operation

Pinout & Package

SI5338K-B05616-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed across the Si5338 family and validated per Skyworks Rev. 1.6 datasheet.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent outputs; each pair configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank; enable mixed-signal voltage domains
VDD	Core supply	1.8/2.5/3.3 V ±10%; powers PLL, logic, and NVM; PSRR optimized for noise immunity
SCL/SDA	I²C interface	Standard bidirectional bus (400 kHz max); supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error
GND / RSVD_GND	Ground terminals	Eight dedicated GND pins including reserved ground; critical for low-jitter signal integrity and EMI control

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external crystals
PCIe Gen 1–4 compliance	Validated total jitter ≤33.6 ps pk-pk (Gen 2) and RMS jitter ≤0.45 ps (Gen 4 common clock), meeting spec at 100 MHz HCSL
Programmable phase offset	±45 ns adjustment per output in <20 ps steps; enables precise skew alignment across multi-lane interfaces (e.g., PCIe, DDR)
Spread spectrum support	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range
Glitchless frequency tuning	Independent FINC/FDEC pins allow real-time 1 ppm-step frequency updates without output interruption or phase discontinuity
Flexible reference inputs	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential references

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Clocking
Use Scenario: 10 GbE/25 GbE switch ASIC requires synchronized 156.25 MHz and 312.5 MHz clocks with sub-1 ps jitter for SerDes lanes and packet processing logic. IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter clocks to PHY, MAC, and CPU subsystems with deterministic inter-output skew. Use Value: Eliminates need for multiple discrete oscillators; enables single-board timing consolidation while meeting IEEE 802.3bj jitter limits.	Use Scenario: Dual-CPU server motherboard needs PCIe Gen 4 common clock (100 MHz) plus reference clocks for CXL, USB4, and SATA controllers. IC Role / Device Role / Timing Role: Primary timing source delivering PCIe-compliant 100 MHz HCSL and auxiliary clocks (e.g., 25 MHz, 125 MHz) from one IC. Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and simplifies BOM by replacing four oscillators with one programmable device.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processor requires 74.25 MHz and 148.5 MHz clocks with tight phase alignment across multiple serializers. IC Role / Device Role / Timing Role: Multi-format clock generator supplying LVDS and HCSL outputs with programmable phase offset for pixel-clock alignment. Use Value: Achieves <100 ps output-to-output skew and supports frame-accurate genlock via I²C-controlled phase tuning.	Use Scenario: High-speed digital pattern generator uses FPGA with multiple clock domains (e.g., 200 MHz system, 800 MHz sampling, 1 GHz ADC). IC Role / Device Role / Timing Role: Configurable clock synthesizer generating exact frequencies from a single 25 MHz crystal reference. Use Value: Enables arbitrary frequency generation (e.g., 793.75 MHz) without custom crystal procurement; reduces design cycle time.

Ethernet Switch Timing

PCIe Gen 4 Server Clocking

Use Scenario: 10 GbE/25 GbE switch ASIC requires synchronized 156.25 MHz and 312.5 MHz clocks with sub-1 ps jitter for SerDes lanes and packet processing logic.

IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter clocks to PHY, MAC, and CPU subsystems with deterministic inter-output skew.

Use Value: Eliminates need for multiple discrete oscillators; enables single-board timing consolidation while meeting IEEE 802.3bj jitter limits.

Use Scenario: Dual-CPU server motherboard needs PCIe Gen 4 common clock (100 MHz) plus reference clocks for CXL, USB4, and SATA controllers.

IC Role / Device Role / Timing Role: Primary timing source delivering PCIe-compliant 100 MHz HCSL and auxiliary clocks (e.g., 25 MHz, 125 MHz) from one IC.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) and simplifies BOM by replacing four oscillators with one programmable device.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processor requires 74.25 MHz and 148.5 MHz clocks with tight phase alignment across multiple serializers.

IC Role / Device Role / Timing Role: Multi-format clock generator supplying LVDS and HCSL outputs with programmable phase offset for pixel-clock alignment.

Use Value: Achieves <100 ps output-to-output skew and supports frame-accurate genlock via I²C-controlled phase tuning.

Use Scenario: High-speed digital pattern generator uses FPGA with multiple clock domains (e.g., 200 MHz system, 800 MHz sampling, 1 GHz ADC).

IC Role / Device Role / Timing Role: Configurable clock synthesizer generating exact frequencies from a single 25 MHz crystal reference.

Use Value: Enables arbitrary frequency generation (e.g., 793.75 MHz) without custom crystal procurement; reduces design cycle time.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05616-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs; larger 32-QFN (5 mm × 5 mm)	Targets higher-density systems requiring >4 clocks or tighter jitter budgets (e.g., 5G baseband, optical transport)	Select when needing ≥8 outputs or sub-0.5 ps jitter; not drop-in due to pin count, package size, and power architecture differences.
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; 3.3 V only; no I²C or phase control	Used in cost-sensitive, static-clock applications where frequency flexibility is unnecessary (e.g., legacy storage controllers)	Choose only for fixed 100/125/156.25 MHz deployments; lacks programmability, spread spectrum, and multi-voltage support of SI5338K-B05616-GMR.

Compared with Si5332A-D05616-GM and ICS8430I-01T, SI5338K-B05616-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for mid-complexity datacom and embedded systems where design reuse and BOM consolidation matter.

Availability

SI5338K-B05616-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 server platforms, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338K-B05616-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast infrastructure - emphasizing jitter performance, multi-format flexibility, and ease of system-level timing validation.

FAQ

What is the maximum output frequency supported by SI5338K-B05616-GMR?

The SI5338K-B05616-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - as confirmed in Table 6 Note 6 of the Skyworks datasheet Rev. 1.6.

Does SI5338K-B05616-GMR support PCIe Gen 4 Common Clock requirements?

Yes, SI5338K-B05616-GMR meets PCIe Gen 4 Common Clock RMS jitter requirements (≤0.45 ps, 10 kHz–50 MHz) when configured for 100 MHz HCSL output, as validated in Table 12 of the Skyworks datasheet Rev. 1.6. It also satisfies Gen 3 SRNS (≤0.32 ps RMS) and Gen 2 total jitter (≤33.6 ps pk-pk).

Can SI5338K-B05616-GMR operate with a 25 MHz crystal reference?

No - SI5338K-B05616-GMR supports external crystals only in the 8–30 MHz range, per Tables 8–11. A 25 MHz crystal falls within that range and is fully supported; the device's internal oscillator circuitry accommodates 25 MHz with recommended 18 pF load capacitance and ≤100 µW drive level.

How is configuration stored and retained on SI5338K-B05616-GMR?

SI5338K-B05616-GMR uses on-chip one-time-programmable (OTP) non-volatile memory to store configuration. After programming via I²C using ClockBuilder Pro, the device boots directly into the saved configuration without host intervention - enabling autonomous operation in unattended systems.

What output formats does SI5338K-B05616-GMR support on its differential outputs?

SI5338K-B05616-GMR supports LVPECL, LVDS, HCSL, and CML on its four differential output pairs (CLK0A/B through CLK3A/B). Each output driver is independently configurable for format and supply voltage (VDDOx), allowing mixed-signal domain clock distribution on a single IC.

SI5338K-B05616-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338K-B05616-GMR FAQ

1.How can I place an order for SI5338K-B05616-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B05616-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B05616-GMR reliable?

The price and inventory of SI5338K-B05616-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B05616-GMR is usually 5 days.

3.What payment methods are accepted for SI5338K-B05616-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B05616-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B05616-GMR?

SI5338K-B05616-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B05616-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B05616-GMR?

For technical support, including SI5338K-B05616-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B05616-GMR requirements.

6.How does Aetrix verify that SI5338K-B05616-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338K-B05616-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B05616-GMR meets industry standards.

7.What is the process for return or replacement of SI5338K-B05616-GMR?

All SI5338K-B05616-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B05616-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B05616-GMR part is unused and in its original packaging.

Return procedure for SI5338K-B05616-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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